All posts by Chris

SPIE Advanced Lithography Symposium 2017 – day 0

Sunday was a beautiful day in San Jose, bright and sunny.  Just a few blocks away, though, last week’s flooding has devastated whole neighborhoods, causing possibly billions of dollars in damage and the evacuation of more than 10,000 people.  Though very close, that disaster seems far away as we begin the SPIE Advanced Lithography Symposium and shift our focus from what nature can do to us to what we can do to harness nature.

Attendance is again at about 2,200 people this year, similar to what it has been for the last eight years.  It’s hard to get a full sense of what this week will teach us, but just a cursory glance at the program reveals same major shifts in emphasis in the lithography world.  The Advanced Lithography Technologies conference, now renamed Emerging Pattern Technologies, has shrunk considerably over the last two years, from 71 orals and 27 posters in 2015, to 27 orals and 14 posters this year.  There are far fewer papers on DSA (directed self-assembly) this year, as well as fewer multibeam e-beam lithography and nanoimprint lithography papers.  DSA’s early promise of “resolution in a bottle” has given way to the hard reality of defectivity for a thermodynamically driven system.  Meanwhile, the EUV community is emphasizing their progress towards manufacturing readiness.  Some hard realities await them as well, though, and talks on line-edge roughness seem to be everywhere.

This gives me the opportunity to advertise my first talk, at 5:40pm on Monday, at the end of the first day of the EUV conference.  I have been invited to give a 40 minute tutorial talk on stochastic-induced roughness.  I believe this is the first time that we’ve had a tutorial talk at the Advanced Lithography symposium, and I am very excited to be giving it.  I hope everyone interested in line-edge roughness will endure the late hour and come and listen.

For those who are interested in the talk but can’t be at the Symposium, I’m excited about SPIE’s new program to capture each presentation on video.  SPIE will be filming the slides and recording the audio for each talk.  For presenters who have given SPIE permission, these talks will then be posted on the SPIE Digital Library as a permanent record of the presentation.  So, if you do miss my tutorial talk, look for it to show up in a few weeks on the Digital Library.

Let the Symposium begin!

SPIE Advanced Lithography Symposium 2017 – a prologue

The week before the annual SPIE Advanced Lithography Symposium is always a busy one for me, but this year it is particularly so.  It’s not just because I am giving a short course and three conference presentations.  And it’s not because I am coauthor on four other talks (that’s a total of seven papers – yikes!).  No, the real reason I am way too busy this week is that yesterday I launched my new company – Fractilia.

Seventeen years ago I sold my lithography simulation company FINLE Technologies, and after five years at KLA-Tencor I settled into the life of the “Gentleman Scientist”.  My goal was to contribute to the science and practice of lithography through my research, teaching, and writing, all the while looking into the problems that I thought were the most interesting.  For the last 10 years that “most interesting problem” has been stochastic-induced roughness.  It is an incredibly interesting, fun, and important topic, and I have written 25 papers since 2009 that I hope have contributed something to our community’s understanding of this vexing problem.  My goal has been to help transform our understanding of stochastics and roughness, so that we can better tackle the problem of reducing it.

Recently, though, I’ve come to understand that the best way for me to realize my vision of making a positive impact on the industry is to commercialize my ideas in software.  So I’ve teamed up with my old partner from the FINLE days, Ed Charrier, to start a new company (Fractilia) and to introduce a new product (MetroLER).

The goal of Fractilia is to bring rigor, accuracy, and ease-of-use to the analysis of stochastic-induced roughness in semiconductor manufacturing and process development.  Fractilia will deliver something I think is currently lacking in the industry:  accurate and repeatable analysis of SEM images to extract the true, unbiased roughness behavior of wafer features.  I think the industry needs this product.  Of course, the market will tell me if I am right.

So, as I have for the last several years, I’ll be giving papers next week on various ways in which the measurement of pattern roughness can go wrong.  I’ll complain about errors in the SEM and how they hide the true roughness behavior on the wafer.  I’ll moan about the statistical difficulties of sampling, aliasing, and biases in our measurements.  But this year I’ll do more than complain – I’ll do something about it.

For the interested reader, here is a recent press article on the new company:

http://semiengineering.com/fractilia-pattern-roughness-metrology/

And here is the company website:  www.fractilia.com

Now, it is back to writing papers.  See you in San Jose!

Semicon Again

I was at Semicon West yesterday, back again for the first time in 15 years.  I have mixed feelings about it.

Semicon West, held each year in San Francisco, is the biggest of the Semicon trade shows, the main source of revenue for the semiconductor equipment and materials supplier group SEMI (http://www.semi.org/).  I remember well my first visit to a SEMI show, Semicon East in Boston about 1985.  That was when the 128 corridor of Boston was thought to rival Silicon Valley (a vain hope at best) and the growing semiconductor industry was still young.  I was young too, and inexperienced, and the Semicon show opened up a world of information and opportunity for me.  I had much to learn.  I also remember exhibiting at Semicon Southwest in Dallas in 1990, a small booth for my even smaller software startup FINLE Technologies.  Through the 1990s I attended Semicon Japan many times, but managed to avoid going to Semicon West (a privilege of being the boss – I sent someone else).

Over time the Semicon shows grew in size and simultaneously became less important.  At its peak (about 2000), the Semicon West show drew 60,000 people.  But even then the relevance of this kind of trade show was declining.  We longer need to roam the aisles of a massive exhibit floor to find out about suppliers and what they have to offer.  We do that with Google now.  The Semicon East and Southwest shows faded away, leaving only West and its foreign counterparts.

Around this time I finally started attending Semicon West – I now had a boss after selling my company to KLA-Tencor, so it was my turn to go.  “Booth duty” was a dirty word at KLA-Tencor, and I presume at most other companies as well.  The only people that came by the booth were competitors, people looking for jobs, and the curious neighboring exhibitors.  Customer meetings were the only reason most of us came, and those took place off the floor.

And then it happened.  My memory is a bit vague, but I think the year was 2001 or 2002 and I think the company was Novellus.  They had a contract for a giant amount of space on the Semicon floor, but they didn’t installing a massive booth with mock-ups of their equipment.  They didn’t send a small army of marketing managers and temp employees (known as “booth babes” in those politically incorrect days).  Instead, Novellus installed a skeletal structure (it looked a bit like a cage) and hung gauzy cloth from the beams.  They installed some monitors that looped marketing presentations.  And they left it completely empty.  Not an employee showed up, and the scene was ghostly.  The message was clear – the trade show was no longer relevant.

Since then, most of the other big suppliers have left as well (Applied Materials, ASML, Lam, KLA-Tencor).  Many of them established off-site events like breakfast forums and technical programs.  The attendance at Semicon West is still large, but only half of its peak.  It’s a trade show for the second tier of semiconductor equipment manufacturers, as well as for the very large number of small suppliers to the suppliers.  SEMI has responded by adding more and more technical programs of their own, and expanding into solar and other related fields.

All the while I avoided coming here (after I returned to my boss-less lifestyle in 2005).  SEMI invited me many times to participate, but I always declined.  Finally, I decided it was time to give the show another chance, and I agreed to moderate Tuesday’s technical session on lithography.  How bad could it be?

Well, it can’t be very bad when you have a good group of speakers.  Lucian Shifren of ARM reminded us that scaling isn’t just about lithography, it impacts the device and the design as well.  He asked what should be an obvious question:  “Because you can make something smaller, should you make it smaller?”  From a lithography perspective, we shrink to get an area benefit.  But we never quite get all the area benefit that we expect.  A 0.7X shrink should give us a 0.5X area reduction, but it rarely does.  Going to restricted design rules causes the area to grow, as does the increase in parasitics and variability that come with shrinking.  If we do go to EUV, stochastic variability will consume even more of the shrink.  While the cost of designing a chip at each new node dramatically increases ($150M for a 10-nm design), the benefits that come from the new node go down.  Shifren predicted that only 5 companies will design chips at the 10-nm node.  Is 28-nm the last good node?

After the ARM talk, we had four of the more traditional supplier talks.  Nikon was represented by Steve Renwick, who described a future of “all of the above lithography”, meaning that we will no longer have one lithography approach that everyone uses for every type of product.  193 immersion will not go away, but it may be supplemented by other approaches such as EUV or DSA.  Ben Rathsack of Tokyo Electron America reiterated that point.  What I found most interesting from his talk was the brief mention of using spacers in a multiple patterning process to create a kind of self-aligned via with significantly improved tolerance to overlay errors.  I think such kinds of innovative ideas are going to be required in a world where variation is a much bigger percentage of the mean.

Mike Lercel gave the ASML talk, where of course everyone was interested in hearing an update on EUV progress.  He said that multiple 125W sources were currently being installed and tested at customer sites.  It is too early to have any availability data on these sources, and experience suggests that availability will ramp slowly.  But that means that 2016 really will be the year when we have “100W by the end of the year”, a prediction first made by Cymer and ASML for 2007 (http://life.lithoguru.com/?p=409).  Chris Lyons of JSR focused on resists for EUV, where he claimed that resolution is not a problem, but we still have a ways to go on the dose/LER trade-off.  Finally, Harry Levinson of GlobalFoundries talked about the readiness of EUV.  He described 2015 as a breakthrough year since, for the first time, a fab could print enough EUV wafers to start process learning.  He suggested that “EUV deserves serious consideration for the 7-nm node.”  Interestingly, he showed a chart of throughput versus EUV source power that had the throughput lower by about a factor of two compared to what ASML typically shows.  Throughput calculations require many assumptions that mostly remain unstated in these kinds of presentations.  Obviously, ASML’s assumptions are much more optimistic that GlobalFoundries’.  I think I trust GlobalFoundries’ assumptions more.

So, in all, the technical talks were good, and I am glad that I attended.  Still, I don’t think Semicon West is for me.  I have no desire to go to the exhibit floor, and I’d rather meet up with lithography colleagues (including sales and marketing folks) at a technical meeting rather than a trade show.  Obviously 30,000 people think the show adds some value to them, it just doesn’t for me.

God is Liquid

My neighbors have been remodeling their house for what seems like forever.  For the last year or so I have noticed the same truck parked in front – a red lowrider with a Virgin Mary statue on the dash, a cross hanging from the rearview mirror, and number of inspirational messages printed on cards stuck in the front of the windshield.  Walking past the other day I noticed a large one, printed in Gothic script.

Christ is the Solid

Rather than consider the possibility of a poor translation from a Spanish phrase, I started taking the message seriously.  Suppose Christ is the solid.  What about the other states of matter?  Of course, the Holy Ghost must be a gas.  Surely, plasma (fire) is Satan.  That leaves one left:  God must be liquid.

So there you have it, a proof based on a very reasonable premise, using mostly unassailable logical principles, worthy of any medieval scholar.  Now to work out the theological ramifications of a god that conforms to its container.

SPIE Advanced Lithography Symposium 2016 – day 4

I bounced all over the conference on Thursday (the last day), from Tim Brunner’s paper predicting focus and overlay performance based on measured wafer bow and thickness, to Derk Brouns’s update on an EUV pellicle.  Nelson Felix of IBM discussed early use of EUV lithography for 10-nm and 7-nm node logic devices (as opposed to the high-k1 results reported by Intel on their 14-nm node).  The data-packed paper deserves much further study and I hope his proceedings paper contains all the information from his presentation.  He mentioned the rule of thumb, commonly discussed this week, that if EUV throughput can get above a reliable 60 wafers per hour, EUV is cost effective compared to combining three 193 immersion patterns.  All such calculations assume many things, not all of which I was able to catch from the talk, that greatly affect the outcome.  I’m sure that equal yield is assumed (a standard assumption for cost calculations), but we also need to know the dose that was assumed.  Nelson mentioned that while printing 36-nm-pitch lines and spaces, going to a dose of 35 mJ/cm2 produced a noticeable yield improvement compared to a 30 mJ/cm2 dose.  I wish that we might see more data like this in the future, since we desperately need to understand the yield/dose trade-off.

Jo Finders of ASML gave an excellent talk, emphasizing what many resist companies don’t quite get:  the quality of the image coming from the scanner matters a lot.  For decades, lithographers have focused on optimizing masks and illumination to maximize the NILS (normalized image log-slope) of the image.  Exposure latitude is proportional to NILS, so every little bit of improvement matters.  Early EUV work was at larger k1 values, and many people were not yet concerned with process windows, so NILS did not get as much attention.  But Jo reminded us of something we should never forget:  LER, LWR and the local critical dimension uniformity (LCDU) that is caused by that roughness are all inversely proportional to NILS.  Thus, for a given resist material at a given exposure dose, the easiest way to lower LER and LCDU is to increase the NILS, using classical approaches like illumination optimization.  Of course, everyone should be following Jo Finder’s advice.  We also have to be aware that any roughness measurements must be made at the same NILS to be comparable – something almost no one does.  The RLS (Resolution-LER-Sensitivity) trade-off should always be NILS corrected.  Another option is to use the LER/LWR resist metric that I proposed, though it seems not to have caught on since I published it in 2014.  Still, that metric is also NILS dependent and so NILS must be controlled in order to make comparisons.  One way to do so is to use a reference image, such as the interferometric images produced at Paul Scherrer Institut.

On another topic, ASML and Nikon described the performance of their latest 193 immersion scanners.  Overlay, focus control, and throughput on these new tools are very impressive.  Tool productivity has increased by a factor of 2 in the last 7 years or so, and I wonder where continued productivity improvements will come from.  A very difficult problem.

The last paper I attended was on detailed characterization of roughness measurements.  My friend and roughness expert Vassilios Constantoudis could not make it this year, so his co-author Hari Pathangi did a good job of delivering the paper for him.  Building on the earlier work of Ricardo Ruiz, this paper explored the correlation of roughness from feature to feature for both SAxP and DSA.  (I hope you have been reading this blog all week, because as you can see I am now dropping acronyms as if I learned them in elementary school).  For these techniques we must look not just at edge-to-edge correlations, but feature-to-feature correlations across multiple pitches.

So what are my impressions of the symposium overall?  This was a year of important but incremental progress.  Let’s look at how various technologies are trending.

Trending Up:

EUV lithography has made important progress over the last year and the mood among many is more positive (especially since two years ago).  Now that the 80W sources in the field are running in a moderately reliable fashion, learning in the fabs has begun in earnest.  ASML has demonstrated a 200W source, but the delta between lab demonstration and reliable performance in the field is a great one.  The key question for the source will be when do customers get their next upgrade?  Will it be 100W by the end of the year?

Nanoimprint lithography (NIL) has made lonely progress at Canon (since they bought Molecular Imprints) and Toshiba, with SK Hynix joining the effort to some extent.  And while serious investment in NIL came years too late, there is still a good chance they will succeed, at least for flash production.

Stochastic awareness seems to have hit critical mass this year.  At the dimensions we are now experiencing, the fundamental stochastics of the world are coming to dominate lithographic behavior.  Stochastics are hard to control, but any hope that we might do so will be through greater theoretical understanding and careful experimental measurements.

Trending Down:

Directed self-assembly (DSA) progress has been disappointing in the last year, though that could be due to my inflated expectations.  It appears that no one is yet using DSA in production, and every head-to-head with a competing method (atomic layer deposition for contact hole shrinks, SAQP for lines and spaces) has favored the incumbent process.

EUV resists switched from excitement about nanoparticle resists to excitement about metal-containing resists.  There is much hope that real progress is just around the corner, but results remain depressingly consistent:  the only way to lower LER is to raise the dose.  Resist developers have not embraced a thorough understanding of stochastics as the foundation of their resist design, and have not internalized Lord Kelvin’s dictum:  if you can’t model it, you don’t understand it.

 

Of course, there were many other things going on at the conference, and I was able to attend only a small fraction of the many talks presented this past week.  As always, I am invigorated by the progress and learning that I have seen, and exhausted by the non-stop intellectual challenges that this symposium provides.  When I hit that post button for this final summary, I’m going to bed.

SPIE Advanced Lithography Symposium 2016 – day 3

On Wednesday morning I again went to see resist talks, but this time in the EUV conference (which is more than a little confusing, but I’m glad I don’t have to work out the details of which paper goes in which conference).  Anna Lio of Intel gave a very nice talk entitled “EUV Resists: What’s Next?”  At the beginning of her talk she repeated the ASML marketing line about the HVM introduction of EUV:  “It’s a matter of when, not if.”  But that statement misses the whole point.  When is a matter of if.  If EUV continues to be delayed, it will very quickly reach the point of not being viable commercially.

That nit aside, it was a great pleasure to here Intel so emphatically promote a stochastic world view when it comes to EUV resists and their performance.  Here is some of what she said:

“Think stochastics first.”

“We need new ideas and new resist platforms for stochastics.”

“Stochastics will rule the world.”

She said that not significantly improving over today’s performance of stochastic-driven local CDU, local edge placement, and roughness is a “deal breaker” for EUV.

I only hope that the audience really listened and absorbed this message.  She had a tone of frustration in her talk that the industry has not taken these ideas sufficiently seriously (I empathize – I only wish that Intel and other EUV customers had preached that message ten years ago).  A reason for that frustration could be found in the next paper where SEMATECH provided historical data of EUV resist performance on a combined metric of resolution, sensitivity, and LER showing that there has been basically no improvement since 2012.  This is not good.

My frustration was extended to the next talk, where I heard again from Japan’s EIDEC (EUVL Infrastructure Development Center) on their “metal resist”.  First, they refuse to say what metal is in their resist.  This knowledge is absolutely necessary, in my opinion, before deciding to take this resist seriously.  Also, they have repeatedly claimed that their resist has both high sensitivity and low LER, but all of their results show either high sensitivity or low LER, but never both.  There is disconnect between their marketing and their data.

The next set of authors, from TOK, had no need to read my post from yesterday where I explained that high resist contrast is a necessary condition for reaching the lowest possible LER at a given dose and feature size.  Their paper was all about how to combine stochastic thinking with conventional resist thinking about high contrast.  I hope the new resist developers were listening to this veteran company.

Togawa-san of Osaka University talked about acid amplifiers and how they might be able to reduce the effects of stochastic variation.  He finally gave an explanation for how acid amplifiers might achieve this that makes sense.  Acid amplifiers essentially multiply the acid concentration by some factor, allowing a lower exposure dose.  Since the acid amplifier achieves higher acid levels, more quencher can be added to the resist formulation (which otherwise would have an unacceptable impact on sensitivity).  The higher quencher levels lead to greater gradients of deprotection levels (or effective acid levels).  But these acid amplifiers can, at best, act like a normal amplifier:  amplifying the noise as well as the signal, plus adding its own noise source as well.  Thus, the relative acid uncertain will go up.  The real question is whether the higher chemical gradient can compensate for the higher acid uncertainty.  The experimental data is ambiguous.  Looks like a place where rigorous modeling could help.

My final comment on the EUV resist talks is about Roberta Fallica of the Paul Scherrer Institut.  This was his first talk at SPIE, and it was a fantastic one.  Not only did he show very good measurements of resist absorption at the EUV wavelength (a difficult thing to do) compared to calculated values, but he proposed a novel way of interpreting their importance.  He described the inverse of the absorption coefficient-dose to clear product as the volume of resist cleared by one absorbed photon.  I’m still trying to wrap my brain around that idea, but it is definitely worth thinking about.

Outside of the resist world, I enjoyed a talk by Andrew Burbine, an RIT student working with Mentor Graphics.  He discussed and implemented the idea of using Bayesian statistics to improve OPC model calibration.  It gave an excellent tutorial on the idea, and provided an initial validation of its value.  This looks like an idea worth pursuing.

In the afternoon Juan de Pablo of the University of Chicago gave an excellent invited talk on directed self-assembly (DSA) modeling.  An while there was a time conflict, I caught half of an invited talk by David Pan (my University of Texas colleague) on how shrinking standard cells makes accessing them (through connections called pins) increasingly difficult.  Thus, we often don’t get the area size benefit from the shrink that we expected.

My favorite quote of the day (heard at a hospitality suite):  “When you take a picture without light, don’t blame the film.” – John Biafore.

On a different topic, someone attending this meeting for the first time asked me why there were so few women here.  This is not a new comment.  While those of us who have worked in the industry and attended this meeting for many years may be used to it, from an outsider’s perspective the lack of gender diversity at the Advanced Lithography Symposium can be jarring.  It is pervasive, from the conference leadership and ranks of SPIE fellows to the speakers and attendees.  It is also true at other lithography meetings that I attend, and I think in the semiconductor workplace as well.  What is it about lithography and the semiconductor industry that attracts so few women?

Finally, since the topic keeps coming up, let me say this:  my Lotus is safe and secure in my garage.  Vivek Bakshi and I resolved our bet on EUV lithography last year, and you can read about it here.

SPIE Advanced Lithography Symposium 2016 – day 2

It is 8 am on Tuesday, and the extreme dilemma that is the SPIE AL Symposium is facing me head on.  Where do I go?  Do I go to the ASML EUV status talk?  Toshiba on the status of nanoimprint for flash manufacturing?  Ben Bunday’s review of metrology challenges at 5 nm?  Or Moshe Preil’s overview of patterning challenges below 10 nm?  Every conference scheduled one of their best talks for first thing in the morning.  I chose none of the above and went to the patterning materials conference.  What a treat!  Six papers in a row full of science, deep dives into mechanisms, data, chemical structures, new measurement approaches, attempts at theoretical explanations, and great discussions.  I saw no graphs with missing axes labels, “resist A vs. resist B” comparisons, spin, or marketing pitches.  It was what I love most about SPIE.  Congratulations to all the authors in that session (and especially the students).

I did manage to make it to a different Toshiba talk later in the morning on the status of nanoimprint lithography (NIL) development towards manufacturing readiness.  Here is the summary.  For 2x-nm flash device manufacturing (that is, devices with half-pitch 20-nm and above), defect levels have undergone continuous improvement such that they are confident that all defect specs will be met before the end of this year.  According to Toshiba, the only thing prevent NIL from going into manufacturing at these nodes is throughput, which is off by around a factor of 2.  Another talk by Canon explained their roadmap for achieving the desired throughput (at least 50-60 wafers per hour for the four-head cluster tool) in the next year by decreasing resist spread time.  NIL is extremely close to a go at that node.

But the value of NIL is not at the 2x-nm flash nodes, where it replaces a mature SADP process.  Instead, it is at the 1x-nm node, where it can replace the more expensive and problematic SAQP.  There, much more work needs to be done.  Defect levels are much too high, both on the as-manufactured templates and during wafer processing.  Progress is also being made here, but two-three more years will be required at the least, I suspect.

I enjoyed a presentation by Gian Lorusso of Imec on attempts to validate LER/LWR metrology accuracy.  What I got out of the talk was basically this:  it is really, really hard.  We know about the many problems of LER measurements using SEMs, but measurements using TEM or AFM are even worse.  Today, we have no alternative but to use our top-down SEM, which means we need to be much more careful about characterizing biases in those measurements and analyzing the data in the most rigorous way possible.

(An aside to all users of LER metrology:  you haven’t measured LER or LWR until you report not just sigma, but the correlation length and roughness exponent as well.  You have no excuse – just do it.)

By the end of a long day I participated in a panel discussion celebrating the 30-year history of the metrology conference.  I have a simple rule for evening panel discussions:  if they are not fun, don’t bother.  This one was fun – thank you Ofer Adan.  The champagne helped as well.  Next week, I’ll try to post my 7-minute talk on the philosophy of metrology.

As a final note for day two, I’ve had a number of people ask me if my skeptical attitude towards the ultimate manufacturing success of EUV lithography has changed.  There has been good progress made in the last year.  The 80W tools in the field have finally become reliable enough to allow engineering development.  Everyone is talking about ASML’s 200W demonstration.  These are all impressive achievements.  But my skepticism remains.  Source power in the field is still just 80W (will we exceed 100W by the end of the year?).  Throughput in the field is enough to peel another layer of the onion and find several more problems with EUV (see yesterday’s post).  And there are many more onion layers to go, with problems as yet undiscovered.  All of these things take time, and time is the enemy of EUV lithography.  EUV has missed the 10-nm node at all companies, and will almost surely miss the 7-nm node at all companies as well.  Will it be ready for the 5-nm node?  A 5-nm node that must be relaxed to accommodate the resolution limits of single patterning EUVL?  Will any fab be able to make money at 5 nm, with or without EUV?  My skepticism remains.