SPIE Microlithography Conference, Day 1 (Monday)

Keynote or Key Node?
The conference began with three fairly good keynote talks. But Yan Borodovsky set me off, inevitably enough, by touch on one of my pet peeves. Intel has for several years now bragged about staying on a two year cycle of technology node advances while the rest of the industry says cycles are slowing to three years. They recently announced a working 45nm node SRAM and industry pundits hailed their technology lead. But what does that mean, exactly, a 45nm node device? Are there any 45nm dimensions involved? Historically (ten years ago or more), the node name was equal to half of the smallest pitch on the critical level (metal 1 usually contains the smallest pitch on the chip since it is the mask level that controls the die size). But that was then. Now, node names have marketing value. Press releases and market analysts extol the importance of getting to the next node. It was inevitable, I suppose – node names became too important to be left to the engineers to define. They’ve been taken over by the marketing departments. So how does Intel define the 45nm node? Very simple – it the technology used two years after they began what they defined as the 65nm node. There’s no magic in the node name, and no information either. So what about pitch, the smallest line/space repeating distance on the chip? It seems that Intel is reducing pitch by about 30% every three years. Go figure.

Leave a Reply

Your email address will not be published.