Ron Schuurhuis of ASML began the day with a review of the improvements they have made to the NXE:3400C, many of them (such as inline tin refill and reduced collector swap times) resulting in fairly significant tool productivity enhancements.  But something else in his presentation has encouraged me to go off on a rant:  calculated throughputs based on unrealistic resist sensitivity assumptions.  In the very early days of EUV, throughput calculations were based on the mythical 5mJ/cm2 (dose-to-size) resist.  After source power increased by something like an order of magnitude, a mythical 10mJ/cm2 resist was introduced for theoretical throughput calculations.  As the source power increased further, ASML grudgingly acknowledged that these unrealistic dose targets would never be met and allowed the theoretical dose for throughput calculations to rise again (to 15 and then 20 mJ/cm2), but always climbing more slowly than source power so that they could still claim a rising throughput.  In the Schuurhuis presentation I saw what appeared to be the next transition, to a 30mJ/cm2 mythical resist.  (As an example, their calculated 170 wafer per hour throughput using a 20 mJ/cm2 resist becomes 135 wph assuming a 30 mJ/cm2 dose-to-size.)  Assuming 30 mJ/cm2 is certainly better than assuming 20, but line/space patterning requires closer to 40 mJ/cm2 at modest pitches (and higher for smaller pitches), and contact holes need over 50mJ/cm2 (to print, for example, 40nmx70nm pitch staggered arrays).  Can we just admit reality for once and start using 40 mJ/cm2 for all future throughput calculations on the 0.33 NA tool?

I was excited by a talk by Rich Wise of Lam Research showing extremely preliminary results for a dry deposited, dry developed metal-organic nanocluster resist.  These early results looked promising.  I always worry that nanocluster resists will not have high enough development contrast (best measured using a focus-exposure process window and mask linearity compared to a standard resist), but I look forward to seeing more from Lam on this material in the future.

Gurpreet Singh of Intel gave a pair of talks on complementing EUV with directed self-assembly (DSA).  (I have to be careful with my spelling – I started to say that DSA was “complimenting” EUV, but in fact the opposite is true).  The first application of DSA was in rectification:  print lousy EUV patterns at a tight pitch (say, 30 nm or 28 nm) and low dose, etch them into an underlayer, then fix the terribly rough features using DSA guided by the underlayer pattern, without pitch division.  This works very well for line/space patterning and could replace an SAQP flow, but of course Intel said nothing about design rule constraints.  Their goal was clear:  improve edge placement error by reducing the pitch walking endemic to SADP and SAQP.  With the low EUV doses possible using this approach, it might even be cost effective.  They used the very mature PS-b-PMMA system since it has the possibility of sufficiently low defectivity for practical manufacturing.  But pushing to smaller pitches (below about 24 nm) will likely require a new material, and he proposed the development of a “modified” PS-b-PMMA system as the best path forward.

From Charlie Liu of IBM I heard my new acronym of the week:  PB&S (print big and shrink).

Hyo Seon Suh of imec updated us on their continuing progress in making DSA practical for high-volume manufacturing (full disclosure – I was a coauthor on this talk).  Through a number of optimizations they were able to shrink the unbiased LER from 3.0 nm to 2.5 nm, while keeping defectivity near the 2/cm2 level.

Customer meetings kept me away from much of the afternoon talks, and as a substitute for the canceled KLA PROLITH party many of us met up in the evening at my new favorite San Jose brewpub, Uproar, where we toasted another successful day advancing lithography.