SPIE Advanced Lithography Symposium 2020 – day 1

The plenary session began with opening remarks and awards.  We welcomed two new Fellows of SPIE:  Hiroshi Fukuda and Mike Rieger.  Congratulations for that well-deserved recognition.  This year’s Frits Zernike Award for Microlithography was given to Winfried Kaiser of Zeiss for his major contributions to 193nm and EUV optics.  He also gets my nomination for most dapper Zernike award winner!  Three good plenary talks (on machine learning, in-memory computing, and Flash memory process technology) were full of interesting technical information (so long as you ignored the commercial embedded in the Kioxia talk).

The opening keynote talk for the EUV conference was given by Charlie Wallace of Intel, where he described not just the current status of EUV lithography for manufacturing 32 nm pitch lines and spaces, but the immense challenges of shrinking the pitch to 30 nm or 28 nm.  As pitch shrinks, higher doses are required, but even at these high doses defect rates are too high.  Some quotes:  “It is execution time for EUV lithography.”  “We need fundamental improvement in EUV materials”.  “Improvement in metrology is required.” 

A quick pause to talk about Intel.  Anyone who has read this blog over the last several years knows that I have complained about the paucity of semiconductor-maker talks at this and other lithography conferences, and especially about how few talks Intel would give.  I must now recognize that this criticism belongs to the past.  Intel has really stepped up their game recently, and they have seven presentations at AL this year.  Thank you, Intel!  The entire lithography community appreciates your contribution.

The Metrology conference opened with an interesting experiment – the first keynote was given remotely.  Alain Diebold of SUNY Polytechnique called in and spoke while his slides were advanced onsite.  While not ideal, it was much better than a cancelled talk and I appreciate the conference chairs thinking experimentally about how to let the talk go on.  Several afternoon talks covered the important topic of edge placement errors and how to characterize them using contour-based metrology rather than the traditional CD-based measurements.  It is clear that this approach is quickly becoming a standard method.  In the EUV session, Marie Krysak of Intel showed again how standard “three-sigma” characterization of stochastic contact hole variations was not good enough to predict chip yield.  She used a combination of non-Gaussian extrapolation and stress tests (underexposing to make the defect rates high enough to measure), both of which produced similar results when comparing the performance of different EUV resists.

Some news:  Canon and (at the very last minute) Qoniac have cancelled their hospitality events.  I still managed to stay out too late and drink too much beer (thank you Fractilia and Inpria).

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