SPIE Advanced Lithography Symposium 2018 – day 2

Midway through the week, my first impressions have solidified into a clear view of the conference themes.  I think we can call this the year of stochastics.  Five years ago it was hard to get anyone to listen when you talked about stochastic effects in lithography, but today it seems to be the only thing people are talking about.  What has changed?  EUV lithography is close enough to reality that people can imagine, and even visualize, using EUV to make something other than test images for their SPIE paper.  We can visualize making devices, devices that must yield.  And it is not a pretty picture.  For years we talked about progress in all the other areas of EUV lithography, with a parting comment that “EUV resists must improve” to fix the stochastic effects.  But now it is clear that we must attempt to make devices with the resists we have today, and no miracles are on the horizon.

The other thing that has changed is the shift in emphasis from stochastic-induced roughness to stochastic-induced defects.  It is hard for us lithographers to understand how an extra nanometer of linewidth roughness might affect our devices, but it easy for us to understand the implications of a missing contact hole.

I started my day in the Metrology conference with a session dedicated to LER/LWR measurement.  Gian Lorusso introduced the “imec protocol”, his attempt to standardize the measurement of roughness (full disclosure:  I was a coauthor).  He began by describing an exercise imec performed where they sent a set of identical wafers to 13 companies and asked them to measure the linewidth roughness and send back the results.  The answers he received varied by +/- 30%.  The need for standardization in measurement is obvious.  The main problem is bias in the measurements due to SEM noise (and how that bias varies with measurement conditions), so the most important recommendation is to always use unbiased measurements.  He also described how the ITRS recommended measurement approach has become outdated with today’s low correlation length processes:  a 2-micron line length is no longer needed.  Gian’s paper is extremely important, and I hope that the imec protocol is widely followed from now on.

My first paper of the conference was in this same session, which included simulation results that were finished the night before (cutting things just a little too close!).

It may seem like I am pitching too many papers that I was a co-author on, but I am going to do it anyway.  Charlotte Cutler of Dow gave an excellent talk on her use of power spectral density analysis to improve resist materials.  As a resist maker, Dow regularly measures features after the lithography step (in industry jargon, ADI:  after develop inspect), but has little access to after-etch results since those depend heavily on each customer’s etch process.  But when it comes to roughness, it is the after-etch performance that matters.  So, Charlotte needs to correlate her ADI measurements to after-etch results.  Traditionally, that has meant looking at the ADI 3-sigma roughness with the assumption that a low ADI 3-sigma roughness would translate into a low after-etch 3-sigma roughness.  Alas, it often does not.  To explore why, she created two matrices of resist formulations and measured the power spectral densities of the roughness of each of them.  She found that while after-develop 3-sigma roughness was not a good predictor of after-etch 3-sigma roughness, the after-develop unbiased PSD(0) was.  I predicted last year that this approach would work (in my EUVL Symposium paper), and it is very gratifying to see this prediction proved out experimentally.

There seem to be fewer ASML papers at the conference this year (is it my imagination?), but I did catch Jan von Schoot talking about their plans for a high-NA EUV scanner.  Every time I see drawing of this tool, or pictures of the lens manufacturing facility under construction at Zeiss, I am amazed at how massive and complicated this tool will be.  Perhaps it is designed to make the NXE:3400 seem only moderately complex.

I walked around the poster session (much smaller than in years past), and saw quite a few good ones.  The conference is now half-way over, but I won’t say it is a downhill ride from here.  Wednesday will be exciting!

5 thoughts on “SPIE Advanced Lithography Symposium 2018 – day 2”

  1. What about the Imprint papers on Tuesday?
    Imprint seems to making excellent progress for Memory. Imprint may still have some issues to resolve–but LER/LWR is not one of them (since the resist is confined/contained in the mask.)
    And I’m still looking for someone to take the other side of my bet ($10K?) that we’ll see a commercial/volume device made with Imprint before EUV.
    And love your SPIE blog every year…

  2. Generate a graph with the Y axis as billions of dollars invested and the X axis the year. Now plot data for both imprint lithography vs EUV lithography. It will look like you only added data for EUV, since the imprint data line will be almost indistinguishable to the x axis.

    1. And on top of that also plot the total industry turnover and profit. And then you have Moore’s Law. It’s not only about investment, it’s about investment versus rewards really. Of course all large companies emphasize the costs and the investments, but what about the rewards and the increasing company and share holder value?

  3. Bob,
    As a technologist (first SPIE paper given in 1985) turned entrepreneur/investor–with plenty of failures and success in both areas–I’ve learned that investing large amounts of money is rarely the best predictor of success–and almost never a good predictor of the best/winning product technical solution. More money is often an attempt to “outspend” a competitor OR to continue funding a product/project that has missed its original promised commercial aviability date. I suspect that the enormous EUV spending is the latter.

    A more relevant graph would be a bar chart showing the amount of money spent (cumulatively by the whole litho eco-system) on each new litho technology that has been successfully implemented (e.g. scanners to steppers to Step-and-Scan, to DUV, to immersion, to DP, etc.) Of course, OK to normalize for size of entire semi industry.

    Then create a second bar chart that also normalizes for either years or number of nodes where the technology is used. This would be a rough relative measure of Return on Investment.

    Then plot where EUV (and imprint, if you like) might fit on these two charts. Feel free to add a outline above the EUV bar (and imprint) on additional spending required.

    I might also include a neighboring bar that normalized for the size of the market (e.g. EUV might only find a home in CPU and Foundry, but not memory, and Imprint might only be NAND.)

    In my suggested version, the EUV bars would still make the imprint data “almost indistinguishable to the x axis,” but EUV might also dwarf ALL the other successively implemented lithography technologies.

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