It is 8 am on Tuesday, and the extreme dilemma that is the SPIE AL Symposium is facing me head on. Where do I go? Do I go to the ASML EUV status talk? Toshiba on the status of nanoimprint for flash manufacturing? Ben Bunday’s review of metrology challenges at 5 nm? Or Moshe Preil’s overview of patterning challenges below 10 nm? Every conference scheduled one of their best talks for first thing in the morning. I chose none of the above and went to the patterning materials conference. What a treat! Six papers in a row full of science, deep dives into mechanisms, data, chemical structures, new measurement approaches, attempts at theoretical explanations, and great discussions. I saw no graphs with missing axes labels, “resist A vs. resist B” comparisons, spin, or marketing pitches. It was what I love most about SPIE. Congratulations to all the authors in that session (and especially the students).
I did manage to make it to a different Toshiba talk later in the morning on the status of nanoimprint lithography (NIL) development towards manufacturing readiness. Here is the summary. For 2x-nm flash device manufacturing (that is, devices with half-pitch 20-nm and above), defect levels have undergone continuous improvement such that they are confident that all defect specs will be met before the end of this year. According to Toshiba, the only thing prevent NIL from going into manufacturing at these nodes is throughput, which is off by around a factor of 2. Another talk by Canon explained their roadmap for achieving the desired throughput (at least 50-60 wafers per hour for the four-head cluster tool) in the next year by decreasing resist spread time. NIL is extremely close to a go at that node.
But the value of NIL is not at the 2x-nm flash nodes, where it replaces a mature SADP process. Instead, it is at the 1x-nm node, where it can replace the more expensive and problematic SAQP. There, much more work needs to be done. Defect levels are much too high, both on the as-manufactured templates and during wafer processing. Progress is also being made here, but two-three more years will be required at the least, I suspect.
I enjoyed a presentation by Gian Lorusso of Imec on attempts to validate LER/LWR metrology accuracy. What I got out of the talk was basically this: it is really, really hard. We know about the many problems of LER measurements using SEMs, but measurements using TEM or AFM are even worse. Today, we have no alternative but to use our top-down SEM, which means we need to be much more careful about characterizing biases in those measurements and analyzing the data in the most rigorous way possible.
(An aside to all users of LER metrology: you haven’t measured LER or LWR until you report not just sigma, but the correlation length and roughness exponent as well. You have no excuse – just do it.)
By the end of a long day I participated in a panel discussion celebrating the 30-year history of the metrology conference. I have a simple rule for evening panel discussions: if they are not fun, don’t bother. This one was fun – thank you Ofer Adan. The champagne helped as well. Next week, I’ll try to post my 7-minute talk on the philosophy of metrology.
As a final note for day two, I’ve had a number of people ask me if my skeptical attitude towards the ultimate manufacturing success of EUV lithography has changed. There has been good progress made in the last year. The 80W tools in the field have finally become reliable enough to allow engineering development. Everyone is talking about ASML’s 200W demonstration. These are all impressive achievements. But my skepticism remains. Source power in the field is still just 80W (will we exceed 100W by the end of the year?). Throughput in the field is enough to peel another layer of the onion and find several more problems with EUV (see yesterday’s post). And there are many more onion layers to go, with problems as yet undiscovered. All of these things take time, and time is the enemy of EUV lithography. EUV has missed the 10-nm node at all companies, and will almost surely miss the 7-nm node at all companies as well. Will it be ready for the 5-nm node? A 5-nm node that must be relaxed to accommodate the resolution limits of single patterning EUVL? Will any fab be able to make money at 5 nm, with or without EUV? My skepticism remains.