I was at Semicon West yesterday, back again for the first time in 15 years. I have mixed feelings about it.
Semicon West, held each year in San Francisco, is the biggest of the Semicon trade shows, the main source of revenue for the semiconductor equipment and materials supplier group SEMI (http://www.semi.org/). I remember well my first visit to a SEMI show, Semicon East in Boston about 1985. That was when the 128 corridor of Boston was thought to rival Silicon Valley (a vain hope at best) and the growing semiconductor industry was still young. I was young too, and inexperienced, and the Semicon show opened up a world of information and opportunity for me. I had much to learn. I also remember exhibiting at Semicon Southwest in Dallas in 1990, a small booth for my even smaller software startup FINLE Technologies. Through the 1990s I attended Semicon Japan many times, but managed to avoid going to Semicon West (a privilege of being the boss – I sent someone else).
Over time the Semicon shows grew in size and simultaneously became less important. At its peak (about 2000), the Semicon West show drew 60,000 people. But even then the relevance of this kind of trade show was declining. We longer need to roam the aisles of a massive exhibit floor to find out about suppliers and what they hve to offer. We do that with Google now. The Semicon East and Southwest shows faded away, leaving only West and its foreign counterparts.
Around this time I finally started attending Semicon West – I now had a boss after selling my company to KLA-Tencor, so it was my turn to go. “Booth duty” was a dirty word at KLA-Tencor, and I presume at most other companies as well. The only people that came by the booth were competitors, people looking for jobs, and the curious neighboring exhibitors. Customer meetings were the only reason most of us came, and those took place off the floor.
And then it happened. My memory is a bit vague, but I think the year was 2001 or 2002 and I think the company was Novellus. They had a contract for a giant amount of space on the Semicon floor, but they didn’t installing a massive booth with mock-ups of their equipment. They didn’t send a small army of marketing managers and temp employees (known as “booth babes” in those politically incorrect days). Instead, Novellus installed a skeletal structure (it looked a bit like a cage) and hung gauzy cloth from the beams. They installed some monitors that looped marketing presentations. And they left it completely empty. Not an employee showed up, and the scene was ghostly. The message was clear – the trade show was no longer relevant.
Since then, most of the other big suppliers have left as well (Applied Materials, ASML, Lam, KLA-Tencor). Many of them established off-site events like breakfast forums and technical programs. The attendance at Semicon West is still large, but only half of its peak. It’s a trade show for the second tier of semiconductor equipment manufacturers, as well as for the very large number of small suppliers to the suppliers. SEMI has responded by adding more and more technical programs of their own, and expanding into solar and other related fields.
All the while I avoided coming here (after I returned to my boss-less lifestyle in 2005). SEMI invited me many times to participate, but I always declined. Finally, I decided it was time to give the show another chance, and I agreed to moderate Tuesday’s technical session on lithography. How bad could it be?
Well, it can’t be very bad when you have a good group of speakers. Lucian Shifren of ARM reminded us that scaling isn’t just about lithography, it impacts the device and the design as well. He asked what should be an obvious question: “Because you can make something smaller, should you make it smaller?” From a lithography perspective, we shrink to get an area benefit. But we never quite get all the area benefit that we expect. A 0.7X shrink should give us a 0.5X area reduction, but it rarely does. Going to restricted design rules causes the area to grow, as does the increase in parasitics and variability that come with shrinking. If we do go to EUV, stochastic variability will consume even more of the shrink. While the cost of designing a chip at each new node dramatically increases ($150M for a 10-nm design), the benefits that come from the new node go down. Shifren predicted that only 5 companies will design chips at the 10-nm node. Is 28-nm the last good node?
After the ARM talk, we had four of the more traditional supplier talks. Nikon was represented by Steve Renwick, who described a future of “all of the above lithography”, meaning that we will no longer have one lithography approach that everyone uses for every type of product. 193 immersion will not go away, but it may be supplemented by other approaches such as EUV or DSA. Ben Rathsack of Tokyo Electron America reiterated that point. What I found most interesting from his talk was the brief mention of using spacers in a multiple patterning process to create a kind of self-aligned via with significantly improved tolerance to overlay errors. I think such kinds of innovative ideas are going to be required in a world where variation is a much bigger percentage of the mean.
Mike Lercel gave the ASML talk, where of course everyone was interested in hearing an update on EUV progress. He said that multiple 125W sources were currently being installed and tested at customer sites. It is too early to have any availability data on these sources, and experience suggests that availability will ramp slowly. But that means that 2016 really will be the year when we have “100W by the end of the year”, a prediction first made by Cymer and ASML for 2007 (http://life.lithoguru.com/?p=409). Chris Lyons of JSR focused on resists for EUV, where he claimed that resolution is not a problem, but we still have a ways to go on the dose/LER trade-off. Finally, Harry Levinson of GlobalFoundries talked about the readiness of EUV. He described 2015 as a breakthrough year since, for the first time, a fab could print enough EUV wafers to start process learning. He suggested that “EUV deserves serious consideration for the 7-nm node.” Interestingly, he showed a chart of throughput versus EUV source power that had the throughput lower by about a factor of two compared to what ASML typically shows. Throughput calculations require many assumptions that mostly remain unstated in these kinds of presentations. Obviously, ASML’s assumptions are much more optimistic that GlobalFoundries’. I think I trust GlobalFoundries’ assumptions more.
So, in all, the technical talks were good, and I am glad that I attended. Still, I don’t think Semicon West is for me. I have no desire to go to the exhibit floor, and I’d rather meet up with lithography colleagues (including sales and marketing folks) at a technical meeting rather than a trade show. Obviously 30,000 people think the show adds some value to them, it just doesn’t for me.