Semicon Again

I was at Semicon West yesterday, back again for the first time in 15 years.  I have mixed feelings about it.

Semicon West, held each year in San Francisco, is the biggest of the Semicon trade shows, the main source of revenue for the semiconductor equipment and materials supplier group SEMI (  I remember well my first visit to a SEMI show, Semicon East in Boston about 1985.  That was when the 128 corridor of Boston was thought to rival Silicon Valley (a vain hope at best) and the growing semiconductor industry was still young.  I was young too, and inexperienced, and the Semicon show opened up a world of information and opportunity for me.  I had much to learn.  I also remember exhibiting at Semicon Southwest in Dallas in 1990, a small booth for my even smaller software startup FINLE Technologies.  Through the 1990s I attended Semicon Japan many times, but managed to avoid going to Semicon West (a privilege of being the boss – I sent someone else).

Over time the Semicon shows grew in size and simultaneously became less important.  At its peak (about 2000), the Semicon West show drew 60,000 people.  But even then the relevance of this kind of trade show was declining.  We longer need to roam the aisles of a massive exhibit floor to find out about suppliers and what they hve to offer.  We do that with Google now.  The Semicon East and Southwest shows faded away, leaving only West and its foreign counterparts.

Around this time I finally started attending Semicon West – I now had a boss after selling my company to KLA-Tencor, so it was my turn to go.  “Booth duty” was a dirty word at KLA-Tencor, and I presume at most other companies as well.  The only people that came by the booth were competitors, people looking for jobs, and the curious neighboring exhibitors.  Customer meetings were the only reason most of us came, and those took place off the floor.

And then it happened.  My memory is a bit vague, but I think the year was 2001 or 2002 and I think the company was Novellus.  They had a contract for a giant amount of space on the Semicon floor, but they didn’t installing a massive booth with mock-ups of their equipment.  They didn’t send a small army of marketing managers and temp employees (known as “booth babes” in those politically incorrect days).  Instead, Novellus installed a skeletal structure (it looked a bit like a cage) and hung gauzy cloth from the beams.  They installed some monitors that looped marketing presentations.  And they left it completely empty.  Not an employee showed up, and the scene was ghostly.  The message was clear – the trade show was no longer relevant.

Since then, most of the other big suppliers have left as well (Applied Materials, ASML, Lam, KLA-Tencor).  Many of them established off-site events like breakfast forums and technical programs.  The attendance at Semicon West is still large, but only half of its peak.  It’s a trade show for the second tier of semiconductor equipment manufacturers, as well as for the very large number of small suppliers to the suppliers.  SEMI has responded by adding more and more technical programs of their own, and expanding into solar and other related fields.

All the while I avoided coming here (after I returned to my boss-less lifestyle in 2005).  SEMI invited me many times to participate, but I always declined.  Finally, I decided it was time to give the show another chance, and I agreed to moderate Tuesday’s technical session on lithography.  How bad could it be?

Well, it can’t be very bad when you have a good group of speakers.  Lucian Shifren of ARM reminded us that scaling isn’t just about lithography, it impacts the device and the design as well.  He asked what should be an obvious question:  “Because you can make something smaller, should you make it smaller?”  From a lithography perspective, we shrink to get an area benefit.  But we never quite get all the area benefit that we expect.  A 0.7X shrink should give us a 0.5X area reduction, but it rarely does.  Going to restricted design rules causes the area to grow, as does the increase in parasitics and variability that come with shrinking.  If we do go to EUV, stochastic variability will consume even more of the shrink.  While the cost of designing a chip at each new node dramatically increases ($150M for a 10-nm design), the benefits that come from the new node go down.  Shifren predicted that only 5 companies will design chips at the 10-nm node.  Is 28-nm the last good node?

After the ARM talk, we had four of the more traditional supplier talks.  Nikon was represented by Steve Renwick, who described a future of “all of the above lithography”, meaning that we will no longer have one lithography approach that everyone uses for every type of product.  193 immersion will not go away, but it may be supplemented by other approaches such as EUV or DSA.  Ben Rathsack of Tokyo Electron America reiterated that point.  What I found most interesting from his talk was the brief mention of using spacers in a multiple patterning process to create a kind of self-aligned via with significantly improved tolerance to overlay errors.  I think such kinds of innovative ideas are going to be required in a world where variation is a much bigger percentage of the mean.

Mike Lercel gave the ASML talk, where of course everyone was interested in hearing an update on EUV progress.  He said that multiple 125W sources were currently being installed and tested at customer sites.  It is too early to have any availability data on these sources, and experience suggests that availability will ramp slowly.  But that means that 2016 really will be the year when we have “100W by the end of the year”, a prediction first made by Cymer and ASML for 2007 (  Chris Lyons of JSR focused on resists for EUV, where he claimed that resolution is not a problem, but we still have a ways to go on the dose/LER trade-off.  Finally, Harry Levinson of GlobalFoundries talked about the readiness of EUV.  He described 2015 as a breakthrough year since, for the first time, a fab could print enough EUV wafers to start process learning.  He suggested that “EUV deserves serious consideration for the 7-nm node.”  Interestingly, he showed a chart of throughput versus EUV source power that had the throughput lower by about a factor of two compared to what ASML typically shows.  Throughput calculations require many assumptions that mostly remain unstated in these kinds of presentations.  Obviously, ASML’s assumptions are much more optimistic that GlobalFoundries’.  I think I trust GlobalFoundries’ assumptions more.

So, in all, the technical talks were good, and I am glad that I attended.  Still, I don’t think Semicon West is for me.  I have no desire to go to the exhibit floor, and I’d rather meet up with lithography colleagues (including sales and marketing folks) at a technical meeting rather than a trade show.  Obviously 30,000 people think the show adds some value to them, it just doesn’t for me.

God is Liquid

My neighbors have been remodeling their house for what seems like forever.  For the last year or so I have noticed the same truck parked in front – a red lowrider with a Virgin Mary statue on the dash, a cross hanging from the rearview mirror, and number of inspirational messages printed on cards stuck in the front of the windshield.  Walking past the other day I noticed a large one, printed in Gothic script.

Christ is the Solid

Rather than consider the possibility of a poor translation from a Spanish phrase, I started taking the message seriously.  Suppose Christ is the solid.  What about the other states of matter?  Of course, the Holy Ghost must be a gas.  Surely, plasma (fire) is Satan.  That leaves one left:  God must be liquid.

So there you have it, a proof based on a very reasonable premise, using mostly unassailable logical principles, worthy of any medieval scholar.  Now to work out the theological ramifications of a god that conforms to its container.

SPIE Advanced Lithography Symposium 2016 – day 4

I bounced all over the conference on Thursday (the last day), from Tim Brunner’s paper predicting focus and overlay performance based on measured wafer bow and thickness, to Derk Brouns’s update on an EUV pellicle.  Nelson Felix of IBM discussed early use of EUV lithography for 10-nm and 7-nm node logic devices (as opposed to the high-k1 results reported by Intel on their 14-nm node).  The data-packed paper deserves much further study and I hope his proceedings paper contains all the information from his presentation.  He mentioned the rule of thumb, commonly discussed this week, that if EUV throughput can get above a reliable 60 wafers per hour, EUV is cost effective compared to combining three 193 immersion patterns.  All such calculations assume many things, not all of which I was able to catch from the talk, that greatly affect the outcome.  I’m sure that equal yield is assumed (a standard assumption for cost calculations), but we also need to know the dose that was assumed.  Nelson mentioned that while printing 36-nm-pitch lines and spaces, going to a dose of 35 mJ/cm2 produced a noticeable yield improvement compared to a 30 mJ/cm2 dose.  I wish that we might see more data like this in the future, since we desperately need to understand the yield/dose trade-off.

Jo Finders of ASML gave an excellent talk, emphasizing what many resist companies don’t quite get:  the quality of the image coming from the scanner matters a lot.  For decades, lithographers have focused on optimizing masks and illumination to maximize the NILS (normalized image log-slope) of the image.  Exposure latitude is proportional to NILS, so every little bit of improvement matters.  Early EUV work was at larger k1 values, and many people were not yet concerned with process windows, so NILS did not get as much attention.  But Jo reminded us of something we should never forget:  LER, LWR and the local critical dimension uniformity (LCDU) that is caused by that roughness are all inversely proportional to NILS.  Thus, for a given resist material at a given exposure dose, the easiest way to lower LER and LCDU is to increase the NILS, using classical approaches like illumination optimization.  Of course, everyone should be following Jo Finder’s advice.  We also have to be aware that any roughness measurements must be made at the same NILS to be comparable – something almost no one does.  The RLS (Resolution-LER-Sensitivity) trade-off should always be NILS corrected.  Another option is to use the LER/LWR resist metric that I proposed, though it seems not to have caught on since I published it in 2014.  Still, that metric is also NILS dependent and so NILS must be controlled in order to make comparisons.  One way to do so is to use a reference image, such as the interferometric images produced at Paul Scherrer Institut.

On another topic, ASML and Nikon described the performance of their latest 193 immersion scanners.  Overlay, focus control, and throughput on these new tools are very impressive.  Tool productivity has increased by a factor of 2 in the last 7 years or so, and I wonder where continued productivity improvements will come from.  A very difficult problem.

The last paper I attended was on detailed characterization of roughness measurements.  My friend and roughness expert Vassilios Constantoudis could not make it this year, so his co-author Hari Pathangi did a good job of delivering the paper for him.  Building on the earlier work of Ricardo Ruiz, this paper explored the correlation of roughness from feature to feature for both SAxP and DSA.  (I hope you have been reading this blog all week, because as you can see I am now dropping acronyms as if I learned them in elementary school).  For these techniques we must look not just at edge-to-edge correlations, but feature-to-feature correlations across multiple pitches.

So what are my impressions of the symposium overall?  This was a year of important but incremental progress.  Let’s look at how various technologies are trending.

Trending Up:

EUV lithography has made important progress over the last year and the mood among many is more positive (especially since two years ago).  Now that the 80W sources in the field are running in a moderately reliable fashion, learning in the fabs has begun in earnest.  ASML has demonstrated a 200W source, but the delta between lab demonstration and reliable performance in the field is a great one.  The key question for the source will be when do customers get their next upgrade?  Will it be 100W by the end of the year?

Nanoimprint lithography (NIL) has made lonely progress at Canon (since they bought Molecular Imprints) and Toshiba, with SK Hynix joining the effort to some extent.  And while serious investment in NIL came years too late, there is still a good chance they will succeed, at least for flash production.

Stochastic awareness seems to have hit critical mass this year.  At the dimensions we are now experiencing, the fundamental stochastics of the world are coming to dominate lithographic behavior.  Stochastics are hard to control, but any hope that we might do so will be through greater theoretical understanding and careful experimental measurements.

Trending Down:

Directed self-assembly (DSA) progress has been disappointing in the last year, though that could be due to my inflated expectations.  It appears that no one is yet using DSA in production, and every head-to-head with a competing method (atomic layer deposition for contact hole shrinks, SAQP for lines and spaces) has favored the incumbent process.

EUV resists switched from excitement about nanoparticle resists to excitement about metal-containing resists.  There is much hope that real progress is just around the corner, but results remain depressingly consistent:  the only way to lower LER is to raise the dose.  Resist developers have not embraced a thorough understanding of stochastics as the foundation of their resist design, and have not internalized Lord Kelvin’s dictum:  if you can’t model it, you don’t understand it.


Of course, there were many other things going on at the conference, and I was able to attend only a small fraction of the many talks presented this past week.  As always, I am invigorated by the progress and learning that I have seen, and exhausted by the non-stop intellectual challenges that this symposium provides.  When I hit that post button for this final summary, I’m going to bed.

SPIE Advanced Lithography Symposium 2016 – day 3

On Wednesday morning I again went to see resist talks, but this time in the EUV conference (which is more than a little confusing, but I’m glad I don’t have to work out the details of which paper goes in which conference).  Anna Lio of Intel gave a very nice talk entitled “EUV Resists: What’s Next?”  At the beginning of her talk she repeated the ASML marketing line about the HVM introduction of EUV:  “It’s a matter of when, not if.”  But that statement misses the whole point.  When is a matter of if.  If EUV continues to be delayed, it will very quickly reach the point of not being viable commercially.

That nit aside, it was a great pleasure to here Intel so emphatically promote a stochastic world view when it comes to EUV resists and their performance.  Here is some of what she said:

“Think stochastics first.”

“We need new ideas and new resist platforms for stochastics.”

“Stochastics will rule the world.”

She said that not significantly improving over today’s performance of stochastic-driven local CDU, local edge placement, and roughness is a “deal breaker” for EUV.

I only hope that the audience really listened and absorbed this message.  She had a tone of frustration in her talk that the industry has not taken these ideas sufficiently seriously (I empathize – I only wish that Intel and other EUV customers had preached that message ten years ago).  A reason for that frustration could be found in the next paper where SEMATECH provided historical data of EUV resist performance on a combined metric of resolution, sensitivity, and LER showing that there has been basically no improvement since 2012.  This is not good.

My frustration was extended to the next talk, where I heard again from Japan’s EIDEC (EUVL Infrastructure Development Center) on their “metal resist”.  First, they refuse to say what metal is in their resist.  This knowledge is absolutely necessary, in my opinion, before deciding to take this resist seriously.  Also, they have repeatedly claimed that their resist has both high sensitivity and low LER, but all of their results show either high sensitivity or low LER, but never both.  There is disconnect between their marketing and their data.

The next set of authors, from TOK, had no need to read my post from yesterday where I explained that high resist contrast is a necessary condition for reaching the lowest possible LER at a given dose and feature size.  Their paper was all about how to combine stochastic thinking with conventional resist thinking about high contrast.  I hope the new resist developers were listening to this veteran company.

Togawa-san of Osaka University talked about acid amplifiers and how they might be able to reduce the effects of stochastic variation.  He finally gave an explanation for how acid amplifiers might achieve this that makes sense.  Acid amplifiers essentially multiply the acid concentration by some factor, allowing a lower exposure dose.  Since the acid amplifier achieves higher acid levels, more quencher can be added to the resist formulation (which otherwise would have an unacceptable impact on sensitivity).  The higher quencher levels lead to greater gradients of deprotection levels (or effective acid levels).  But these acid amplifiers can, at best, act like a normal amplifier:  amplifying the noise as well as the signal, plus adding its own noise source as well.  Thus, the relative acid uncertain will go up.  The real question is whether the higher chemical gradient can compensate for the higher acid uncertainty.  The experimental data is ambiguous.  Looks like a place where rigorous modeling could help.

My final comment on the EUV resist talks is about Roberta Fallica of the Paul Scherrer Institut.  This was his first talk at SPIE, and it was a fantastic one.  Not only did he show very good measurements of resist absorption at the EUV wavelength (a difficult thing to do) compared to calculated values, but he proposed a novel way of interpreting their importance.  He described the inverse of the absorption coefficient-dose to clear product as the volume of resist cleared by one absorbed photon.  I’m still trying to wrap my brain around that idea, but it is definitely worth thinking about.

Outside of the resist world, I enjoyed a talk by Andrew Burbine, an RIT student working with Mentor Graphics.  He discussed and implemented the idea of using Bayesian statistics to improve OPC model calibration.  It gave an excellent tutorial on the idea, and provided an initial validation of its value.  This looks like an idea worth pursuing.

In the afternoon Juan de Pablo of the University of Chicago gave an excellent invited talk on directed self-assembly (DSA) modeling.  An while there was a time conflict, I caught half of an invited talk by David Pan (my University of Texas colleague) on how shrinking standard cells makes accessing them (through connections called pins) increasingly difficult.  Thus, we often don’t get the area size benefit from the shrink that we expected.

My favorite quote of the day (heard at a hospitality suite):  “When you take a picture without light, don’t blame the film.” – John Biafore.

On a different topic, someone attending this meeting for the first time asked me why there were so few women here.  This is not a new comment.  While those of us who have worked in the industry and attended this meeting for many years may be used to it, from an outsider’s perspective the lack of gender diversity at the Advanced Lithography Symposium can be jarring.  It is pervasive, from the conference leadership and ranks of SPIE fellows to the speakers and attendees.  It is also true at other lithography meetings that I attend, and I think in the semiconductor workplace as well.  What is it about lithography and the semiconductor industry that attracts so few women?

Finally, since the topic keeps coming up, let me say this:  my Lotus is safe and secure in my garage.  Vivek Bakshi and I resolved our bet on EUV lithography last year, and you can read about it here.

SPIE Advanced Lithography Symposium 2016 – day 2

It is 8 am on Tuesday, and the extreme dilemma that is the SPIE AL Symposium is facing me head on.  Where do I go?  Do I go to the ASML EUV status talk?  Toshiba on the status of nanoimprint for flash manufacturing?  Ben Bunday’s review of metrology challenges at 5 nm?  Or Moshe Preil’s overview of patterning challenges below 10 nm?  Every conference scheduled one of their best talks for first thing in the morning.  I chose none of the above and went to the patterning materials conference.  What a treat!  Six papers in a row full of science, deep dives into mechanisms, data, chemical structures, new measurement approaches, attempts at theoretical explanations, and great discussions.  I saw no graphs with missing axes labels, “resist A vs. resist B” comparisons, spin, or marketing pitches.  It was what I love most about SPIE.  Congratulations to all the authors in that session (and especially the students).

I did manage to make it to a different Toshiba talk later in the morning on the status of nanoimprint lithography (NIL) development towards manufacturing readiness.  Here is the summary.  For 2x-nm flash device manufacturing (that is, devices with half-pitch 20-nm and above), defect levels have undergone continuous improvement such that they are confident that all defect specs will be met before the end of this year.  According to Toshiba, the only thing prevent NIL from going into manufacturing at these nodes is throughput, which is off by around a factor of 2.  Another talk by Canon explained their roadmap for achieving the desired throughput (at least 50-60 wafers per hour for the four-head cluster tool) in the next year by decreasing resist spread time.  NIL is extremely close to a go at that node.

But the value of NIL is not at the 2x-nm flash nodes, where it replaces a mature SADP process.  Instead, it is at the 1x-nm node, where it can replace the more expensive and problematic SAQP.  There, much more work needs to be done.  Defect levels are much too high, both on the as-manufactured templates and during wafer processing.  Progress is also being made here, but two-three more years will be required at the least, I suspect.

I enjoyed a presentation by Gian Lorusso of Imec on attempts to validate LER/LWR metrology accuracy.  What I got out of the talk was basically this:  it is really, really hard.  We know about the many problems of LER measurements using SEMs, but measurements using TEM or AFM are even worse.  Today, we have no alternative but to use our top-down SEM, which means we need to be much more careful about characterizing biases in those measurements and analyzing the data in the most rigorous way possible.

(An aside to all users of LER metrology:  you haven’t measured LER or LWR until you report not just sigma, but the correlation length and roughness exponent as well.  You have no excuse – just do it.)

By the end of a long day I participated in a panel discussion celebrating the 30-year history of the metrology conference.  I have a simple rule for evening panel discussions:  if they are not fun, don’t bother.  This one was fun – thank you Ofer Adan.  The champagne helped as well.  Next week, I’ll try to post my 7-minute talk on the philosophy of metrology.

As a final note for day two, I’ve had a number of people ask me if my skeptical attitude towards the ultimate manufacturing success of EUV lithography has changed.  There has been good progress made in the last year.  The 80W tools in the field have finally become reliable enough to allow engineering development.  Everyone is talking about ASML’s 200W demonstration.  These are all impressive achievements.  But my skepticism remains.  Source power in the field is still just 80W (will we exceed 100W by the end of the year?).  Throughput in the field is enough to peel another layer of the onion and find several more problems with EUV (see yesterday’s post).  And there are many more onion layers to go, with problems as yet undiscovered.  All of these things take time, and time is the enemy of EUV lithography.  EUV has missed the 10-nm node at all companies, and will almost surely miss the 7-nm node at all companies as well.  Will it be ready for the 5-nm node?  A 5-nm node that must be relaxed to accommodate the resolution limits of single patterning EUVL?  Will any fab be able to make money at 5 nm, with or without EUV?  My skepticism remains.

SPIE Advanced Lithography Symposium 2016 – day 1

At 8 am on Monday, the conference begins with opening remarks and the plenary session.

Bill Arnold and Harry Levinson won a “Special Contribution Award to the Art and Science of Lithography” for their two-part paper “Focus: the Critical Parameter for Submicron Lithography” published in 1988.  I read and cited those papers frequently over the years, and I still recall the clarity of their arguments and the insightfulness of their approach.  Without a doubt, these were milestone papers in the development of modern microlithography thought and practice.

Dr.  Andreas Erdmann of the Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB (Germany) became our newest fellow.  Kurt Ronse of Imec was also promoted to that rank, but he was unable to attend the symposium this year and will receive his recognition at a later conference.

The symposium awards were completed when Yan Borodovsky, recently retired from Intel, become the 13th Frits Zernike Award winner.  Congratulations to all of them!

Some years, the plenary speakers are chosen from outside the lithography community to bring perspective and breadth to the opening of the symposium.  This year, we heard from three of our own.  Harry Levinson of GlobalFoundries gave an historical perspective on research and developments in lithography.  He mentioned the low uptime (60-70%) of early excimer lasers and the immaturity of deep-UV resists (especially sensitivity to airborne contaminants) as motivations for the extension of i-line lithography in the early 1990s.  The obvious analogy to EUV lithography was left unstated.  Two good quotes from Harry’s talk:

“Computer programming became a required skill for leading-edge lithography” (discussing the importance of computational lithography).

“Issues at the molecular scale will need to be addressed to realize the optical resolution “entitlement” of EUV lithography.”

Richard Gottscho, EVP of Lam Research, discussed deposition and etching and how those technologies will evolve to improve control in the age of multiple patterning.  In particular, the move towards atomic layer deposition (ALD) and now atomic layer etching (ALE) are greatly improving uniformity and control, though at the cost of processing speed.  These processes work by saturating the wafer with a monolayer of reactive species, which then is reacted to produce the deposition or etching.  This saturation is self-limiting and so removes many process variables from being significant factors in the process rate, easing both the process development and process control burdens.

Tony Yen of TSMC gave a very nice historical perspective on the development of EUV, one that he believes has put EUV lithography on the “eve of manufacturing”.  The very first demonstration of EUV lithography (called soft x-ray lithography until 1993) was by Hiroo Kinoshita in 1986, followed soon by Obert Wood and his many collaborators at AT&T Bell Labs.  Significant government and industry funding began in 1992 and the EUV LLC was formed in 1997 to pool the growing industry and government efforts in EUV.  With the completion of an important prototype tool, the 0.1 NA Engineering Test Stand, development work on the exposure tool shifted to ASML.  They produced their alpha-demo tool (ADT) in 2006, the NXE:3100 in 2011, and shipped the NXE:3300 in 2013.  Tony finished his historical description by saying that their first NXE:3350 has recently arrived at the TSMC loading dock.

As for the current status of EUV lithography at TSMC, Tony confirmed that the plan of record is to exercise EUV at the 7-nm node and use it in production at the 5-nm node.  The remaining problems include mask blank defectivity (currently about 20/blank, too high to use for metal patterning, but maybe OK for contact holes) and the still unproven pellicle solution.  Resist sensitivity in now closer to an acceptable range (between 25 and 30 mJ/cm2 for lines and spaces and between 35 and 40 for contact holes), but with unacceptably high linewidth roughness (LWR).

The invited talks at the EUV lithography conference gave some further perspective from Intel and Samsung on the readiness of EUV for high volume manufacturing (HVM).  Apparently, one of the big issues last year was the reliability of the tin droplet generator, part of the EUV light source.  Both Intel and Samsung were very pleased about progress on that front, so that source reliability has reached 70%, enough to do real engineering work with the tools, though not enough for manufacturing.  Intel reported end-of-line yield loss due to particles added to the mask during use.  They saw an average of one killer defect added per 20 reticle-stage-load cycles, a level that makes manufacturing impossible without a pellicle.

Seong-Sue Kim also reported on the mixed successes and failures of EUV at Samsung in the last year.  They reported 3 particle adders on the mask for every 10,000 wafers printed, a number too high by an order of magnitude at least.  But more disturbing was his report of mask damage after 40,000 wafer exposures using the 80W source.  Blisters formed within the mask multilayer, some of which popped.  Not only was the mask ruined, but contamination travelled through the optical system and made its way to the wafer.  I worry that such chemical reactions induced by the energetic photons of EUV light will behave nonlinearly with intensity.  How bad will this become when using a 250W source?

On the resist front, everyone is talking about metal oxide resists for EUV.  For many years now, Inpria has used metal oxides as an EUV resist that could deliver high resolution and low LWR, but at doses of 80 mJ/cm2 – too high to be practical given the realities of low EUV source power.  The push to get sensitivities of these resists into the 30 mJ/cm2 range has now been successful but, surprise!, the LWR is much worse.  It seems that all attempts to defy the laws of physics through chemistry continue to be unsuccessful.  Yet, since we do not have a complete understanding of all aspects of LER formation, the physical limits of roughness are unknown.  If other problems can be solved, metal oxide resists may be the way to go.

Indulge me, if you will, on another rant.  Thirty years ago I would come to this conference and see papers by resist companies that all had a familiar pattern:  here is our new material, here is a cartoon of the mechanism of why it will work, and here are one or two SEM images of high resolution patterns.  Success is then claimed.  What we learned painfully over time is that high resolution demonstrations of a material are a necessary but not sufficient condition of success.  The reason is the simple fact that a very good aerial image can produce a decent image in a mediocre resist.  The projected image maters!  So how do you know if your material is any good?  You have to consider the development contrast of the resist and how it affects process latitude.  A high image contrast can produce a good single image in a low contrast resist, but cannot produce good exposure latitude.  One needs to compare exposure latitude (or better yet, the focus-exposure process window – see the mention of the Arnold and Levinson papers above) to the entitlement process latitude (that which could be obtained from an ideal, infinite contrast resist), or at least to the current resist of record.  This lesson was learned and over the next 20 years resist contrast was systematically raised until it become sufficiently high.  Today, we almost take high resist contrast for granted (at 193 immersion, at least).

It seems that this lesson has been forgotten.  Have we experienced high-contrast resists for so long that we have forgotten how a low-contrast resist behaves?  Have we forgotten how to measure or characterize resist contrast?  I almost never see a process window for an EUV resist.  I never see a comparison of the exposure latitude to the NILS (or the best exposure latitude possible).  People compare resists printed at different numerical apertures without considering the differences in the aerial images that exposure them, or don’t even mention the conditions at which the patterns were imaged, as if a 20-nm pattern is a function of the resist alone.  We need high sensitivity EUV resists.  We need low LWR.  But we also need high resist contrast.  Let’s start measuring and reporting that, please.

One of my favorite quotes of the day: “I never thought they would discover gravity waves before EUV made it into manufacturing.”  – Kenneth Goldberg (Note:  over $1B was spent over 40 years on the gravity wave effort.)

And my favorite mixed metaphor: “We have only scratched the tip of the iceberg.” – Alex Vaglio Pret

SPIE Advanced Lithography Symposium 2016 – a prologue

2016 will prove to be a pivotal year in the history of semiconductor lithography.  How do I know this?  Because every year proves to be a pivotal year in the history of lithography.  Why should 2016 be any different?  Our industry moves too fast to allow a slack year.

I am frequently reminded of Sturtevant’s Law, not just because it is cute and funny (though it is), but because behind the humor lies a profound truth.  Sturtevant’s Law says that the end of optical lithography is 6 – 7 years away.  Always has been, always will be.  When I started in the field of lithography way back in 1983, Sturtevant’s Law was as yet unformulated but nonetheless in full swing.  X-ray or e-beam lithography was sure to take over by 1990 since it was obvious that optical lithography could not cross the 1 micron barrier.

This was but one of many, many failed predictions of the end of optical lithography.  But the fundamental truth behind Sturtevant’s Law is this:  we always know what we are doing for the next node (in 2 – 3 years), and are pretty sure about the node after that, but we have almost no visibility into what comes next.  We know all of the unsolved problems looming beyond the 6 year horizon, and can’t quite picture the solutions.  Sturtevant’s Law is a statement about our research and development timelines and how they relate to the pace of Moore’s Law.

But while Sturtevant’s Law has been in force for over 30 years, I’m afraid that it may be coming to an untimely end.  The reason is simple:  we no longer have good visibility out to two nodes (6 years).  We have a just barely reasonable impression about what the next node will bring, and are sure that the node after that is impossible.  The end of optical lithography is no longer 6 -7 years away, it is 2 – 3 years away, and even that time frame seems impossibly distant and opaque.

Our angst is about more than just lithography.  Of course, we lithographers know that the industry moves to the pace that we set.  Still, it is disconcerting to believe that a slowdown in lithography means the end of Moore’s Law.  Yet that is what is at stake.  In 2016, we must discover a path that keeps Moore’s Law moving forward, or watch Moore’s Law fall flat.

But a slowdown of Moore’s Law has already begun.  Intel’s 14-nm node was a year late, and Intel has admitted that its 10-nm node will also be late, on a 3-year node pace rather than the historic 2-year cycle.  TSMC has not admitted the slow-down, but is experiencing it anyway.  They created a “faux” node, a 16-nm product line that has the same dimensions and density as the previous 20-nm node.  Revealingly, when the 16-nm node came online last year, they did not report the revenues of that node separately as had been their normal practice, but rather began to lump the 16 and 20-nm node revenues together in one bucket.  “Follow the money” was good advice coming from Deep Throat, and is good advice in the semiconductor industry as well.

Moore’s Law is slowing down because lithography is not keeping up.  Multiple patterning is expensive and process control is a serious problem.  No other solutions are available.  Now, this where EUV is supposed to come in and save the day, right?

Alas, EUV is late.  ASML has made very good progress in the last two years, but that progress has been enough to keep EUV late, not enough to catch up with the industry need.  Anyone who has read these conference blogs before knows that I have been and continue to be an EUV skeptic.  But for the first time in over 20 years of development, I finally see a glimmer of hope for EUV.

Time is the enemy of all lithography development programs.  The demands of lithography move at an unrelenting pace, and even the slightest schedule slip in a lithography development program is the kiss of death.  EUV is late, an almost unmistakable sign of failure, and yet finally there is hope.  And here is the reason.

EUV was supposed to save Moore’s Law.  But instead, the slowdown of Moore’s Law may save EUV.

The 10-nm node will be two years late compared to the original schedule (naming games aside), as we are now on a three-year Moore’s Law cycle.  But since EUV is more than two years late, it still could not impact that node.  How late will the 7-nm node be?  Could it be late enough to use EUV?  That is a distinct possibility.

The big picture of lithography is bigger than the picture we will see at the SPIE Advanced Lithography Symposium in 2016, since the big picture involves the macroeconomics of the semiconductor industry itself.  But what we will see here this week is still big and very important.  How painful is multiple patterning really?  How close is directed self-assembly to being production worthy?  What is the status of nanoimprint manufacturing for Flash production?  Has there been any progress in taming the roughness beast?  And of course, what about EUV source power?

There are always many questions coming into the start of the SPIE lithography conference.  I am excited to start learning the answers.

Running: I can still do it

Ten years ago I took up running as a sport, and found that I really liked it.  I ran two marathons, seven half marathons, and some 10Ks.  All was good; I was meeting my goals and improving my times, until I hurt my knee.  I had cartilage repair surgery, just before a major study showed that these surgeries worked no better than physical therapy alone.  Ah well.  That was five years ago, and I had several abortive attempts to start running again, always followed quickly by a re-injury of that knee.  Finally, a slow and deliberate recovery coupled with weight training of the muscles around the knee allowed a comeback.  This week I ran my first race in five years – the 3M Half Marathon.

I wasn’t sure what to expect.  My goal was to beat 2 hours, so I chose a pace just fast enough to make that time and very carefully stuck to that pace through the whole race.  I kept waiting to poop out, but the miles went by and I never did.  My last two miles were my fastest, and I finished the race at 1:58:35.  That’s only 4 minutes slower than my most recent 3M half of five years ago – an acceptable age-related slowdown!

Incidentally, I ran a 10K five years ago with the goal of running it in my age in minutes, something I accomplished to within three seconds.  For this week’s half marathon I ran two 10Ks back to back, and the second one had a time of 55:11.  That’s 30 seconds faster than my age!  I’m back.

Musings of a Gentleman Scientist