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Semiconductor Microlithography

SPIE Advanced Lithography Symposium Postscript

It is 10 days since the SPIE Advanced Lithography Symposium, and I have finally finished and submitted all my papers!  If you are interested in any of them, you can find them on the Fractilia website here:

https://www.fractilia.com/technology/

Note that for the tutorial talk I gave I will not be preparing a paper, but you can get a copy of the slides I presented.  And for those you who didn’t attend the talk, this is the way it ended:

 

SPIE Advanced Lithography Symposium 2017 – day 4

In the second talk of the morning in the EUV session, Andrew Liang of Lam Research showed how much work it takes to optimize a new process, and how that work can pay off.  Local critical dimension uniformity (LCDU) is a term that refers to stochastic-induced variation in CD.  Conventionally, CDU looks at the variation of CD across a chip, exposure field, wafer, and lot caused by things like mask CD variation, film variations across the wafer, focus control across the exposure field, hotplate temperature uniformity, and many other factors.  The length scale of these variations tend to be quite large compared to the pitch of the patterns being printed, so that two feature next to each other are assumed to be largely affected in the same way by all of these variations.  Stochastic variations, on the other hand, have a length scale (called the correlation length) that is small compared to the feature size so that we can understand its impact by looking at any features, even ones right next to each other.  By measuring the CDU of a small group features (a 7X7 array of contact holes, for example) we can isolate the stochastic impact on CD uniformity from the other CDU factors.  This is the idea behind LCDU.

Liang optimized the hard mask below the resist by switching to a thinner PECVD film, optimized the lithography process to maximize the image log-slope, and optimized the etch process using atomic layer etching.  The last item is the most interesting to me, since it looks like it is possible to use an etch rate that varies as a function of aspect ratio to compensate for resist CD variation.  When the resist CD is too small, the aspect ratio of the hole is higher.  For a typical etch process, this higher aspect ratio would cause shadowing of the etchant and a reduction in etch rate, making the small hole even smaller.  But etching can also involve polymer deposition on feature sidewalls to slow etching down.  If that polymer deposition slows down with higher aspect ratio, maybe it is possible to increase the etch rate when contact holes are too small, thus improving the LCDU.  To me this seems like magic, but only in the sense of Arthur C. Clarke’s third law, “Any sufficiently advanced technology is indistinguishable from magic.”  Others have reported on this very exciting possibility, and I am looking forward to learning more.

Ravi Bonam of IBM collected a large amount of data from a programmed roughness mask, a mask that contained an added rectangle (jog) along the feature edge of varying size and frequency.  By measuring the mask and the wafer after printing, something can be learned about the optical transfer of roughness from the mask to the wafer, and the ability of wafer metrology to see roughness at specific frequencies.  Unfortunately his data analysis and presentation left me unable to grasp a single lesson learned from his data.  I’ll have to wait for the manuscript.

Tom Wallow gave a comprehensive overview of sources of metrology variation for the case of metrology used for OPC model calibration.  His two laments were the same as from every lithography model developer.  First, customers want models to fit the data better than the data uncertainty justifies.  Second, models that are based on physics require data that has accuracy, not just precision.  Historically, metrologists have focused on precision for the simple reason that accuracy is just too hard a problem to comprehend.  Tom, I hope people absorb your lessons, but don’t hold your breath.

I presented my last paper at 2pm, and then I was mostly done for the day.  After giving my last demo of Fractilia’s new MetroLER software, socializing with friends that I rarely see at other times throughout the year became my last priority of the conference.  I sampled only about 10 – 15% of the papers in the symposium, and I learned a tremendous amount from them.  I dub this year’s major theme to be stochastics, and I am glad for the attention that it is finally receiving.  I’ll go home with many ideas to investigate and try out.  For anyone interested in my papers and presentations, I’ll be posting them soon on my lithoguru website, and also on the new Fractilia website.  But first I’m going home to relax.

SPIE Advanced Lithography Symposium 2017 – day 3

It is just me or is 8:00am too early for the first technical talk of the day?  At least on Wednesday the 8:00am talk was an excellent one.  Oktay Yildirim of ASML presented a basic but very useful roughness model.  Alas, I had to run out before the end of his paper to give my own paper in the metrology session.  The problem with stochastics becoming the major theme of this year’s conference is that there have been stochastics papers everywhere, often conflicting with each other.  The morning metrology session was all roughness measurement.  Of course, I was pleased with Barton Lane’s presentation of SEM errors and their impact on roughness measurements, but since I was a coauthor that is to be expected.  I also gave my own paper on a new method for roughness characterization – the level crossing method.  I was especially impressed with Dr. Serap Savari’s work on applying modern algorithmic techniques for power spectral density (PSD) estimation.  I guess I’m going to have to figure out what a discrete prolate spheroidal sequence is.

Ravi Bonan of IBM went back to an old idea that remains underutilized today – the programed roughness mask.  Similarly, Sergey Babin of aBeam created a metrology test structure with deterministic randomness.  Please don’t ask me to explain.  The core concept of both is the same – create small structures with programmed “roughness” to test our measurement and analysis capabilities.  More creative ideas in these regards will certainly be welcome.

A creative idea came from Harm Dillen of ASML.  He used an array of very dense contact holes to measure the field distortion of scanning electron microscope images.  His application was edge placement error measurement, but as Barton Lane described earlier it also impacts roughness measurements.  Modeling the distortion using a typical first-order overlay model allows the systematic contribution (about 0.6 nm RMS for his data) to be subtracted out.  This amount of distortion is enough to have a quite noticeable on line-edge roughness measurement.  I can’t wait to try this method out.

Alex Robinson of Irresistible Materials gave a talk on increasing the sensitivity of EUV resists.  I didn’t attend.  But he did corner me later and run through it with me.  His cartoon chemistry looked very interesting – a believable mechanism for achieving second order acid amplification chemistry.  Now that such chemistry looks possible, I’ll have to think about the roughness implications more carefully.  That’s the problem with stochastics – nothing is obvious the first time you think about it.

The evening ended with another round of excellent hospitality suites (thanks to all of the companies that feed me so well throughout the week), with the PROLITH party always being my favorite.  For all of you who have asked me if my new company (Fractilia) will revive the traditional bathtub party of my old company (FINLE), the answer is no.  The bathtub party must remain the stuff of lithography legend; Fractilia will create its own traditions.

SPIE Advanced Lithography Symposium 2017 – day 0

Sunday was a beautiful day in San Jose, bright and sunny.  Just a few blocks away, though, last week’s flooding has devastated whole neighborhoods, causing possibly billions of dollars in damage and the evacuation of more than 10,000 people.  Though very close, that disaster seems far away as we begin the SPIE Advanced Lithography Symposium and shift our focus from what nature can do to us to what we can do to harness nature.

Attendance is again at about 2,200 people this year, similar to what it has been for the last eight years.  It’s hard to get a full sense of what this week will teach us, but just a cursory glance at the program reveals same major shifts in emphasis in the lithography world.  The Advanced Lithography Technologies conference, now renamed Emerging Pattern Technologies, has shrunk considerably over the last two years, from 71 orals and 27 posters in 2015, to 27 orals and 14 posters this year.  There are far fewer papers on DSA (directed self-assembly) this year, as well as fewer multibeam e-beam lithography and nanoimprint lithography papers.  DSA’s early promise of “resolution in a bottle” has given way to the hard reality of defectivity for a thermodynamically driven system.  Meanwhile, the EUV community is emphasizing their progress towards manufacturing readiness.  Some hard realities await them as well, though, and talks on line-edge roughness seem to be everywhere.

This gives me the opportunity to advertise my first talk, at 5:40pm on Monday, at the end of the first day of the EUV conference.  I have been invited to give a 40 minute tutorial talk on stochastic-induced roughness.  I believe this is the first time that we’ve had a tutorial talk at the Advanced Lithography symposium, and I am very excited to be giving it.  I hope everyone interested in line-edge roughness will endure the late hour and come and listen.

For those who are interested in the talk but can’t be at the Symposium, I’m excited about SPIE’s new program to capture each presentation on video.  SPIE will be filming the slides and recording the audio for each talk.  For presenters who have given SPIE permission, these talks will then be posted on the SPIE Digital Library as a permanent record of the presentation.  So, if you do miss my tutorial talk, look for it to show up in a few weeks on the Digital Library.

Let the Symposium begin!

SPIE Advanced Lithography Symposium 2016 – day 4

I bounced all over the conference on Thursday (the last day), from Tim Brunner’s paper predicting focus and overlay performance based on measured wafer bow and thickness, to Derk Brouns’s update on an EUV pellicle.  Nelson Felix of IBM discussed early use of EUV lithography for 10-nm and 7-nm node logic devices (as opposed to the high-k1 results reported by Intel on their 14-nm node).  The data-packed paper deserves much further study and I hope his proceedings paper contains all the information from his presentation.  He mentioned the rule of thumb, commonly discussed this week, that if EUV throughput can get above a reliable 60 wafers per hour, EUV is cost effective compared to combining three 193 immersion patterns.  All such calculations assume many things, not all of which I was able to catch from the talk, that greatly affect the outcome.  I’m sure that equal yield is assumed (a standard assumption for cost calculations), but we also need to know the dose that was assumed.  Nelson mentioned that while printing 36-nm-pitch lines and spaces, going to a dose of 35 mJ/cm2 produced a noticeable yield improvement compared to a 30 mJ/cm2 dose.  I wish that we might see more data like this in the future, since we desperately need to understand the yield/dose trade-off.

Jo Finders of ASML gave an excellent talk, emphasizing what many resist companies don’t quite get:  the quality of the image coming from the scanner matters a lot.  For decades, lithographers have focused on optimizing masks and illumination to maximize the NILS (normalized image log-slope) of the image.  Exposure latitude is proportional to NILS, so every little bit of improvement matters.  Early EUV work was at larger k1 values, and many people were not yet concerned with process windows, so NILS did not get as much attention.  But Jo reminded us of something we should never forget:  LER, LWR and the local critical dimension uniformity (LCDU) that is caused by that roughness are all inversely proportional to NILS.  Thus, for a given resist material at a given exposure dose, the easiest way to lower LER and LCDU is to increase the NILS, using classical approaches like illumination optimization.  Of course, everyone should be following Jo Finder’s advice.  We also have to be aware that any roughness measurements must be made at the same NILS to be comparable – something almost no one does.  The RLS (Resolution-LER-Sensitivity) trade-off should always be NILS corrected.  Another option is to use the LER/LWR resist metric that I proposed, though it seems not to have caught on since I published it in 2014.  Still, that metric is also NILS dependent and so NILS must be controlled in order to make comparisons.  One way to do so is to use a reference image, such as the interferometric images produced at Paul Scherrer Institut.

On another topic, ASML and Nikon described the performance of their latest 193 immersion scanners.  Overlay, focus control, and throughput on these new tools are very impressive.  Tool productivity has increased by a factor of 2 in the last 7 years or so, and I wonder where continued productivity improvements will come from.  A very difficult problem.

The last paper I attended was on detailed characterization of roughness measurements.  My friend and roughness expert Vassilios Constantoudis could not make it this year, so his co-author Hari Pathangi did a good job of delivering the paper for him.  Building on the earlier work of Ricardo Ruiz, this paper explored the correlation of roughness from feature to feature for both SAxP and DSA.  (I hope you have been reading this blog all week, because as you can see I am now dropping acronyms as if I learned them in elementary school).  For these techniques we must look not just at edge-to-edge correlations, but feature-to-feature correlations across multiple pitches.

So what are my impressions of the symposium overall?  This was a year of important but incremental progress.  Let’s look at how various technologies are trending.

Trending Up:

EUV lithography has made important progress over the last year and the mood among many is more positive (especially since two years ago).  Now that the 80W sources in the field are running in a moderately reliable fashion, learning in the fabs has begun in earnest.  ASML has demonstrated a 200W source, but the delta between lab demonstration and reliable performance in the field is a great one.  The key question for the source will be when do customers get their next upgrade?  Will it be 100W by the end of the year?

Nanoimprint lithography (NIL) has made lonely progress at Canon (since they bought Molecular Imprints) and Toshiba, with SK Hynix joining the effort to some extent.  And while serious investment in NIL came years too late, there is still a good chance they will succeed, at least for flash production.

Stochastic awareness seems to have hit critical mass this year.  At the dimensions we are now experiencing, the fundamental stochastics of the world are coming to dominate lithographic behavior.  Stochastics are hard to control, but any hope that we might do so will be through greater theoretical understanding and careful experimental measurements.

Trending Down:

Directed self-assembly (DSA) progress has been disappointing in the last year, though that could be due to my inflated expectations.  It appears that no one is yet using DSA in production, and every head-to-head with a competing method (atomic layer deposition for contact hole shrinks, SAQP for lines and spaces) has favored the incumbent process.

EUV resists switched from excitement about nanoparticle resists to excitement about metal-containing resists.  There is much hope that real progress is just around the corner, but results remain depressingly consistent:  the only way to lower LER is to raise the dose.  Resist developers have not embraced a thorough understanding of stochastics as the foundation of their resist design, and have not internalized Lord Kelvin’s dictum:  if you can’t model it, you don’t understand it.

 

Of course, there were many other things going on at the conference, and I was able to attend only a small fraction of the many talks presented this past week.  As always, I am invigorated by the progress and learning that I have seen, and exhausted by the non-stop intellectual challenges that this symposium provides.  When I hit that post button for this final summary, I’m going to bed.

SPIE Advanced Lithography Symposium 2016 – day 2

It is 8 am on Tuesday, and the extreme dilemma that is the SPIE AL Symposium is facing me head on.  Where do I go?  Do I go to the ASML EUV status talk?  Toshiba on the status of nanoimprint for flash manufacturing?  Ben Bunday’s review of metrology challenges at 5 nm?  Or Moshe Preil’s overview of patterning challenges below 10 nm?  Every conference scheduled one of their best talks for first thing in the morning.  I chose none of the above and went to the patterning materials conference.  What a treat!  Six papers in a row full of science, deep dives into mechanisms, data, chemical structures, new measurement approaches, attempts at theoretical explanations, and great discussions.  I saw no graphs with missing axes labels, “resist A vs. resist B” comparisons, spin, or marketing pitches.  It was what I love most about SPIE.  Congratulations to all the authors in that session (and especially the students).

I did manage to make it to a different Toshiba talk later in the morning on the status of nanoimprint lithography (NIL) development towards manufacturing readiness.  Here is the summary.  For 2x-nm flash device manufacturing (that is, devices with half-pitch 20-nm and above), defect levels have undergone continuous improvement such that they are confident that all defect specs will be met before the end of this year.  According to Toshiba, the only thing prevent NIL from going into manufacturing at these nodes is throughput, which is off by around a factor of 2.  Another talk by Canon explained their roadmap for achieving the desired throughput (at least 50-60 wafers per hour for the four-head cluster tool) in the next year by decreasing resist spread time.  NIL is extremely close to a go at that node.

But the value of NIL is not at the 2x-nm flash nodes, where it replaces a mature SADP process.  Instead, it is at the 1x-nm node, where it can replace the more expensive and problematic SAQP.  There, much more work needs to be done.  Defect levels are much too high, both on the as-manufactured templates and during wafer processing.  Progress is also being made here, but two-three more years will be required at the least, I suspect.

I enjoyed a presentation by Gian Lorusso of Imec on attempts to validate LER/LWR metrology accuracy.  What I got out of the talk was basically this:  it is really, really hard.  We know about the many problems of LER measurements using SEMs, but measurements using TEM or AFM are even worse.  Today, we have no alternative but to use our top-down SEM, which means we need to be much more careful about characterizing biases in those measurements and analyzing the data in the most rigorous way possible.

(An aside to all users of LER metrology:  you haven’t measured LER or LWR until you report not just sigma, but the correlation length and roughness exponent as well.  You have no excuse – just do it.)

By the end of a long day I participated in a panel discussion celebrating the 30-year history of the metrology conference.  I have a simple rule for evening panel discussions:  if they are not fun, don’t bother.  This one was fun – thank you Ofer Adan.  The champagne helped as well.  Next week, I’ll try to post my 7-minute talk on the philosophy of metrology.

As a final note for day two, I’ve had a number of people ask me if my skeptical attitude towards the ultimate manufacturing success of EUV lithography has changed.  There has been good progress made in the last year.  The 80W tools in the field have finally become reliable enough to allow engineering development.  Everyone is talking about ASML’s 200W demonstration.  These are all impressive achievements.  But my skepticism remains.  Source power in the field is still just 80W (will we exceed 100W by the end of the year?).  Throughput in the field is enough to peel another layer of the onion and find several more problems with EUV (see yesterday’s post).  And there are many more onion layers to go, with problems as yet undiscovered.  All of these things take time, and time is the enemy of EUV lithography.  EUV has missed the 10-nm node at all companies, and will almost surely miss the 7-nm node at all companies as well.  Will it be ready for the 5-nm node?  A 5-nm node that must be relaxed to accommodate the resolution limits of single patterning EUVL?  Will any fab be able to make money at 5 nm, with or without EUV?  My skepticism remains.

SPIE Advanced Lithography Symposium 2016 – day 1

At 8 am on Monday, the conference begins with opening remarks and the plenary session.

Bill Arnold and Harry Levinson won a “Special Contribution Award to the Art and Science of Lithography” for their two-part paper “Focus: the Critical Parameter for Submicron Lithography” published in 1988.  I read and cited those papers frequently over the years, and I still recall the clarity of their arguments and the insightfulness of their approach.  Without a doubt, these were milestone papers in the development of modern microlithography thought and practice.

Dr.  Andreas Erdmann of the Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB (Germany) became our newest fellow.  Kurt Ronse of Imec was also promoted to that rank, but he was unable to attend the symposium this year and will receive his recognition at a later conference.

The symposium awards were completed when Yan Borodovsky, recently retired from Intel, become the 13th Frits Zernike Award winner.  Congratulations to all of them!

Some years, the plenary speakers are chosen from outside the lithography community to bring perspective and breadth to the opening of the symposium.  This year, we heard from three of our own.  Harry Levinson of GlobalFoundries gave an historical perspective on research and developments in lithography.  He mentioned the low uptime (60-70%) of early excimer lasers and the immaturity of deep-UV resists (especially sensitivity to airborne contaminants) as motivations for the extension of i-line lithography in the early 1990s.  The obvious analogy to EUV lithography was left unstated.  Two good quotes from Harry’s talk:

“Computer programming became a required skill for leading-edge lithography” (discussing the importance of computational lithography).

“Issues at the molecular scale will need to be addressed to realize the optical resolution “entitlement” of EUV lithography.”

Richard Gottscho, EVP of Lam Research, discussed deposition and etching and how those technologies will evolve to improve control in the age of multiple patterning.  In particular, the move towards atomic layer deposition (ALD) and now atomic layer etching (ALE) are greatly improving uniformity and control, though at the cost of processing speed.  These processes work by saturating the wafer with a monolayer of reactive species, which then is reacted to produce the deposition or etching.  This saturation is self-limiting and so removes many process variables from being significant factors in the process rate, easing both the process development and process control burdens.

Tony Yen of TSMC gave a very nice historical perspective on the development of EUV, one that he believes has put EUV lithography on the “eve of manufacturing”.  The very first demonstration of EUV lithography (called soft x-ray lithography until 1993) was by Hiroo Kinoshita in 1986, followed soon by Obert Wood and his many collaborators at AT&T Bell Labs.  Significant government and industry funding began in 1992 and the EUV LLC was formed in 1997 to pool the growing industry and government efforts in EUV.  With the completion of an important prototype tool, the 0.1 NA Engineering Test Stand, development work on the exposure tool shifted to ASML.  They produced their alpha-demo tool (ADT) in 2006, the NXE:3100 in 2011, and shipped the NXE:3300 in 2013.  Tony finished his historical description by saying that their first NXE:3350 has recently arrived at the TSMC loading dock.

As for the current status of EUV lithography at TSMC, Tony confirmed that the plan of record is to exercise EUV at the 7-nm node and use it in production at the 5-nm node.  The remaining problems include mask blank defectivity (currently about 20/blank, too high to use for metal patterning, but maybe OK for contact holes) and the still unproven pellicle solution.  Resist sensitivity in now closer to an acceptable range (between 25 and 30 mJ/cm2 for lines and spaces and between 35 and 40 for contact holes), but with unacceptably high linewidth roughness (LWR).

The invited talks at the EUV lithography conference gave some further perspective from Intel and Samsung on the readiness of EUV for high volume manufacturing (HVM).  Apparently, one of the big issues last year was the reliability of the tin droplet generator, part of the EUV light source.  Both Intel and Samsung were very pleased about progress on that front, so that source reliability has reached 70%, enough to do real engineering work with the tools, though not enough for manufacturing.  Intel reported end-of-line yield loss due to particles added to the mask during use.  They saw an average of one killer defect added per 20 reticle-stage-load cycles, a level that makes manufacturing impossible without a pellicle.

Seong-Sue Kim also reported on the mixed successes and failures of EUV at Samsung in the last year.  They reported 3 particle adders on the mask for every 10,000 wafers printed, a number too high by an order of magnitude at least.  But more disturbing was his report of mask damage after 40,000 wafer exposures using the 80W source.  Blisters formed within the mask multilayer, some of which popped.  Not only was the mask ruined, but contamination travelled through the optical system and made its way to the wafer.  I worry that such chemical reactions induced by the energetic photons of EUV light will behave nonlinearly with intensity.  How bad will this become when using a 250W source?

On the resist front, everyone is talking about metal oxide resists for EUV.  For many years now, Inpria has used metal oxides as an EUV resist that could deliver high resolution and low LWR, but at doses of 80 mJ/cm2 – too high to be practical given the realities of low EUV source power.  The push to get sensitivities of these resists into the 30 mJ/cm2 range has now been successful but, surprise!, the LWR is much worse.  It seems that all attempts to defy the laws of physics through chemistry continue to be unsuccessful.  Yet, since we do not have a complete understanding of all aspects of LER formation, the physical limits of roughness are unknown.  If other problems can be solved, metal oxide resists may be the way to go.

Indulge me, if you will, on another rant.  Thirty years ago I would come to this conference and see papers by resist companies that all had a familiar pattern:  here is our new material, here is a cartoon of the mechanism of why it will work, and here are one or two SEM images of high resolution patterns.  Success is then claimed.  What we learned painfully over time is that high resolution demonstrations of a material are a necessary but not sufficient condition of success.  The reason is the simple fact that a very good aerial image can produce a decent image in a mediocre resist.  The projected image maters!  So how do you know if your material is any good?  You have to consider the development contrast of the resist and how it affects process latitude.  A high image contrast can produce a good single image in a low contrast resist, but cannot produce good exposure latitude.  One needs to compare exposure latitude (or better yet, the focus-exposure process window – see the mention of the Arnold and Levinson papers above) to the entitlement process latitude (that which could be obtained from an ideal, infinite contrast resist), or at least to the current resist of record.  This lesson was learned and over the next 20 years resist contrast was systematically raised until it become sufficiently high.  Today, we almost take high resist contrast for granted (at 193 immersion, at least).

It seems that this lesson has been forgotten.  Have we experienced high-contrast resists for so long that we have forgotten how a low-contrast resist behaves?  Have we forgotten how to measure or characterize resist contrast?  I almost never see a process window for an EUV resist.  I never see a comparison of the exposure latitude to the NILS (or the best exposure latitude possible).  People compare resists printed at different numerical apertures without considering the differences in the aerial images that exposure them, or don’t even mention the conditions at which the patterns were imaged, as if a 20-nm pattern is a function of the resist alone.  We need high sensitivity EUV resists.  We need low LWR.  But we also need high resist contrast.  Let’s start measuring and reporting that, please.

One of my favorite quotes of the day: “I never thought they would discover gravity waves before EUV made it into manufacturing.”  – Kenneth Goldberg (Note:  over $1B was spent over 40 years on the gravity wave effort.)

And my favorite mixed metaphor: “We have only scratched the tip of the iceberg.” – Alex Vaglio Pret

SPIE Advanced Lithography Symposium 2016 – a prologue

2016 will prove to be a pivotal year in the history of semiconductor lithography.  How do I know this?  Because every year proves to be a pivotal year in the history of lithography.  Why should 2016 be any different?  Our industry moves too fast to allow a slack year.

I am frequently reminded of Sturtevant’s Law, not just because it is cute and funny (though it is), but because behind the humor lies a profound truth.  Sturtevant’s Law says that the end of optical lithography is 6 – 7 years away.  Always has been, always will be.  When I started in the field of lithography way back in 1983, Sturtevant’s Law was as yet unformulated but nonetheless in full swing.  X-ray or e-beam lithography was sure to take over by 1990 since it was obvious that optical lithography could not cross the 1 micron barrier.

This was but one of many, many failed predictions of the end of optical lithography.  But the fundamental truth behind Sturtevant’s Law is this:  we always know what we are doing for the next node (in 2 – 3 years), and are pretty sure about the node after that, but we have almost no visibility into what comes next.  We know all of the unsolved problems looming beyond the 6 year horizon, and can’t quite picture the solutions.  Sturtevant’s Law is a statement about our research and development timelines and how they relate to the pace of Moore’s Law.

But while Sturtevant’s Law has been in force for over 30 years, I’m afraid that it may be coming to an untimely end.  The reason is simple:  we no longer have good visibility out to two nodes (6 years).  We have a just barely reasonable impression about what the next node will bring, and are sure that the node after that is impossible.  The end of optical lithography is no longer 6 -7 years away, it is 2 – 3 years away, and even that time frame seems impossibly distant and opaque.

Our angst is about more than just lithography.  Of course, we lithographers know that the industry moves to the pace that we set.  Still, it is disconcerting to believe that a slowdown in lithography means the end of Moore’s Law.  Yet that is what is at stake.  In 2016, we must discover a path that keeps Moore’s Law moving forward, or watch Moore’s Law fall flat.

But a slowdown of Moore’s Law has already begun.  Intel’s 14-nm node was a year late, and Intel has admitted that its 10-nm node will also be late, on a 3-year node pace rather than the historic 2-year cycle.  TSMC has not admitted the slow-down, but is experiencing it anyway.  They created a “faux” node, a 16-nm product line that has the same dimensions and density as the previous 20-nm node.  Revealingly, when the 16-nm node came online last year, they did not report the revenues of that node separately as had been their normal practice, but rather began to lump the 16 and 20-nm node revenues together in one bucket.  “Follow the money” was good advice coming from Deep Throat, and is good advice in the semiconductor industry as well.

Moore’s Law is slowing down because lithography is not keeping up.  Multiple patterning is expensive and process control is a serious problem.  No other solutions are available.  Now, this where EUV is supposed to come in and save the day, right?

Alas, EUV is late.  ASML has made very good progress in the last two years, but that progress has been enough to keep EUV late, not enough to catch up with the industry need.  Anyone who has read these conference blogs before knows that I have been and continue to be an EUV skeptic.  But for the first time in over 20 years of development, I finally see a glimmer of hope for EUV.

Time is the enemy of all lithography development programs.  The demands of lithography move at an unrelenting pace, and even the slightest schedule slip in a lithography development program is the kiss of death.  EUV is late, an almost unmistakable sign of failure, and yet finally there is hope.  And here is the reason.

EUV was supposed to save Moore’s Law.  But instead, the slowdown of Moore’s Law may save EUV.

The 10-nm node will be two years late compared to the original schedule (naming games aside), as we are now on a three-year Moore’s Law cycle.  But since EUV is more than two years late, it still could not impact that node.  How late will the 7-nm node be?  Could it be late enough to use EUV?  That is a distinct possibility.

The big picture of lithography is bigger than the picture we will see at the SPIE Advanced Lithography Symposium in 2016, since the big picture involves the macroeconomics of the semiconductor industry itself.  But what we will see here this week is still big and very important.  How painful is multiple patterning really?  How close is directed self-assembly to being production worthy?  What is the status of nanoimprint manufacturing for Flash production?  Has there been any progress in taming the roughness beast?  And of course, what about EUV source power?

There are always many questions coming into the start of the SPIE lithography conference.  I am excited to start learning the answers.

SPIE Advanced Lithography 2015 – day 4

On Thursday I was EUV focused. My first complaint is that there were too many ASML papers. Of course, this is not ASML’s fault. They are doing most of the important work in this field. Still, some sessions started to feel like an ASML meeting rather than an SPIE meeting.

The first session was directed to high numerical aperture (NA) designs for EUV, and the ASML/Zeiss anamorphic imaging approach looks like a good idea. Current lens designs can’t scale to NA > 0.5 because they result in angles hitting the mask on the order of 9° rather than the current 6°. These higher angles degrade imaging performance, removing most of the advantage of the higher NA. Higher magnification (8X) would fix this, but would result in either much larger mask sizes (an unlikely scenario) or much smaller field sizes (1/4 to be specific). The smaller field size would hit EUV where it hurts most: throughput.

The Zeiss/ASML solution is to have an 8X magnification in the direction needed to lower the incident angles on the mask (the scan direction), keeping the magnification 4X in the slit direction. This results in field sizes 1/2 of the current size, a more manageable problem. And by moving to a design with a central obscuration, the angles on the mirrors are reduced as well, increasing mirror reflectivity and overall optics transmission. To keep the projector at six mirrors, the higher NA will require extreme aspheres, a daunting manufacturing challenge. But as Bernhard Kneer of Zeiss said, in perfect Teutonic style, “Zeiss can do this.” I love it.

I’m pleased to see ASML acknowledge that higher resolution will require higher dose for EUV. They projected a need for 60 mJ/cm2 for 8-nm half pitch. They are also beginning to grapple with the hard problem of stochastics, framing the issue as an overlay (or edge placement) problem rather than a CD control (LWR) problem. An afternoon talk by Jan Mulkens provided a scenario where edge placement errors caused by stochastics were about of equal magnitude as those caused by overlay errors. I agree that this is a very valuable way of looking at the problem.

I did manage to sneak out of the EUV sessions to visit the world of DFM (design for manufacturing) and hear Andrew Burbine of Mentor talk about the Akaike Information Criterion for evaluating model performance. Finally! I teach about this criterion, as well as other model evaluation criteria, in a statistics course I give at the University of Texas. It is quite standard practice in many fields of model calibration, and is taught as a best practice in most textbooks on the topic. It is good to see it come into the field of OPC model calibration. Kudos to Mentor. Now if they can just get their customers to think about such metrics, as well as 4-fold validation, as better judges of model quality than just RMS fit error.

I have a new award: for the talk with the best last-minute title change. From Imec,

Original title: “No More of Moore’s Law: the high cost of dimensional scaling”
New title: “Maintaining Moore’s Law: enabling cost-friendly dimensional scaling”

Do you think an angry boss might have been involved in this change of heart?

Here is my summary of the reported progress in EUV. ASML rolled out their 40W source to the NXE:3300s in the field last year, and it is now the standard source for most of those users. TSMC got the first 80W source late last year, and that tool is operating mostly as expected, but with only 55% availability. The result is about 40 wafers per hour using a 23.5 mJ/cm2 dose. Cymer has shown a bench source operating at 110W for one hour, but the much anticipated 250W source is still a long ways away. I suspect we’ll see a 100W source in the hands of a customer by the end of the year.

This is good progress. Is it enough? Everyone admits that EUV has missed the window for insertion at 10 nm (except maybe the investor relations team at ASML). What will it take to have EUV established as the plan of record for 7 nm? It will take even faster progress this year. I wish the hard working folks at ASML good luck.

Many people ask me what the most exciting or revolutionary idea was this year at SPIE. But that is not really the point. Sure, every now and then some really new idea seems to come out of nowhere and take off. I first mentioned in my 2010 conference blog that DSA was starting to look less like a science project and more like a technology. But it is the accumulation of progress on DSA over the last 5 years that is the real story. And this year is like most years: a year of incremental progress. Like Moore’s Law itself, where 50 years of incremental progress have resulted in revolutionary changes in capability, our incremental progress is best viewed as accumulated progress. We push hard every year, and over the years the change is absolutely remarkable. I enjoyed watching that progress reported here this week. And I’m sure I’ll enjoy it even more next year.