Category Archives: Microlithography

Semiconductor Microlithography

Lithography in the Land of Fortified Wine

43rd International Conference on Micro and Nanoengineering (MNE 2017)
September 18-22, 2017, Braga, Portugal

I love port.  The fortified wine is lovely before or after dinner, and makes me feel more sophisticated and refined than I deserve.  Port is made exclusively in the Duoro Valley of northeastern Portugal, then aged in wooden barrels in the coastal city of Porto.  I’ve always wanted to visit there, so when I discovered that the 2017 MNE (Micro and Nanoengineering) conference was being held in Portugal, I made a plan to attend.

I’ve been to MNE twice before, in Leuven and Grenoble, but that was many years ago.  This conference is much like the 3-beams (EIPBN) conference in the US, or the MNC (microprocess and nanotechnology conference) in Asia:  academic, nanotechnology oriented, with some lithography content (though diminishing over the years).  The timing of the conference was good this year, because I was just finishing up a joint project with Gian Lorusso and his team at imec (Belgium) and we needed a venue to publish our work.  MNE fit the bill.

The conference was held in the small northern town of Braga, chosen because it is home to the brand new International Iberian Nanotechnology Lab (INL), where the conference was held.  With about 800 people in attendance (and 535 oral and poster papers), it is a vibrant and growing conference.  So much so that the MNE community has decided to create a new professional society to manage itself.  This was announced for the first time at the conference, and I’m not sure any of us know what that means.

I thought that two of the best talks were the two opening plenary talks.  The first, by Frank Schuurmans, was on the history of ASML plus a discussion of EUV (extreme ultraviolet) lithography.  There was nothing new there for me, but it was good for this academic audience to see what could happen when the multibillion-dollar might of the corporate world is applied to a difficult technical problem.  Olivier Joubert is an academic with a foot in industry, working at CEA-Leti but heavily involved with Applied Materials.  His plenary talk on trends in plasma etching was definitely the best plasma etch talk I’ve ever heard.  The two big drivers for etch technology today are Flash, requiring very high ion energy to dig deep holes, and FinFETs, requiring very low ion energy to prevent damage.  The third driver is the growing list materials that need to be etched.  He discussed line-edge roughness (my favorite topic), proposing that UV light from the plasma is the main cause of the smoothing that occurs during etch.  He also said “There are very few places in the world where you can accurately measure linewidth roughness.”

The plenary talks were held at the elegant and historic Theatro Circo in downtown Braga, and between the two talks was an “artistic performance.”  The performance was modern dance (some of it in cleanroom bunny suits), music incorporating sounds recorded at INL, and a surrealistic video based on scanning electron microscope images.  It sounds weird, but it was fantastic!  The group of performers worked with the INL “artist in residence”, a position as valuable as it is unexpected.  I hope more organizations follow what I hope will be a trend and establish artist in residence programs.

That afternoon Victor Blanco of imec gave a keynote talk “EUV insertion at the N5 node”.  It was the same talk I had heard the week before from Greg McIntyre at the EUVL Symposium in Monterey, but it was great for this audience to hear what the semiconductor industry is doing and what our challenges are.

On Wednesday I enjoyed a talk by Lars-Erik Wernerson of Lund University, Sweden, on progress towards vertical nanowire transistors using alternate channel materials.  It is good to see progress being made on what I suspect will be the future transistor architecture of mainstream logic devices.  Naomi Halas of Rice University gave a fabulous talk on the use of metallic nanoparticles for various sustainability initiatives.  Her talk made clear how many amazingly interesting and important projects can make use of nanofabrication (not just boring old semiconductors).

The conference banquet on Wednesday night was held in a port wine cellar in Porto, with my first (but not last) exposure to the port wine making process.  It was a great dinner, but in the tradition of the region finished very late into the night.  It was hard to get up for the first talks the next morning.

On Thursday I enjoyed a talk by Mark Schvartzman on nanodumbbells (if you’re curious, look them up).  Thursday also had a few interesting metrology papers, but overall the overlap between the content of the conference and my interests was not terribly large.  I gave my paper as a poster on Tuesday, and by Thursday I was saturated with as much nanotechnology as I could absorb.  I decided to play hooky on Friday, skipping the conference in favor of visiting Porto.  I got to downtown about noon and went straight to the port cellars.  Seven hours, five cellars, and 27 tastings of port later I declared the last day of the conference a success.

Photopolymers in Japan

34th International Conference of Photopolymer Science and Technology
Chiba, Japan, June 26 – 29, 2017

Until this year, I had never been to the photopolymer conference (technically known as the International Conference of Photopolymer Science and Technology).  Many of my resist friends have told me for years how good it was, but I never seemed to have the proper motivation (or excuse) to go.  Until this year.  I was invited to give a keynote talk in the computation lithography session at exactly the time I needed to go to Japan to visit customers to promote the imminent release of my new company’s first product.  Synergy happened.

And so, I found myself in Tokyo, a city I greatly enjoy and have missed (since I stopped traveling nonstop 12 years ago, coinciding with my entry into the life of a gentleman scientist).  The photopolymers conference is moderately small and slightly international (this year was typical with 295 attendees, 240 of which were from Japan).  There are three parallel sessions (two in English, one in Japanese), with strong but not exclusive focus on materials and processes for semiconductor lithography.

The conference began with a special talk by Paul Nealey of the University of Chicago, who received an outstanding achievement award from the conference’s sponsoring society for his seminal contributions to the field of directed self-assembly (DSA).  It was an excellent talk by a person who well deserved the honor bestowed on him.

I enjoyed Danilo De Simone’s talk on “Photo Material Readiness at the Eve of EUVL HVM” (EUVL = extreme ultraviolet lithography, HVM = high volume manufacturing, Eve = some unknown date in the future).  Danilo did not explicitly state the answer to his title’s query, so I will:  not ready.  Robert Brainard did answer the query in the title of his talk “What We Don’t Know about EUV Exposure Mechanisms”: a lot.  Patrick Naulleau gave a great talk (as always), explaining well why stochastic-induced linewidth errors are not Gaussian distributed (they have very fat tails).

One of the most interesting ideas I learned about was lithography post-processing using “sequential infiltration synthesis”:  after forming a resist feature, deposit a material (such as alumina) that can subsequently infiltrate the resist to create a network, then plasma ash the resist to reveal just the network.  Yes, the overall roughness was lower (based on biased roughness measurements that I don’t believe), but the interesting thing was the correlation between the left and right edges of the feature.  The original resist feature had uncorrelated edges (the LWR was about 40% larger than the LER), but post processing there was considerable correlation between the edges (the LWR and LER were about equal).  This means that the network created inside the feature stretched from edge to edge.  Fascinating, though thanks to the 65% line shrinkage I’m not sure it’s useful.

Tuesday ended with a panel discussion on EUV insertion into high volume manufacturing.  The panelist presentations were quite predictable, expressing optimism while pointing out the well-known gaps.  As expected, the ASML presentation was the most optimistic, claiming manufacturing insertion for EUV as early as the second half of 2018.  That is one year away!  I laughed out loud when I heard that.  When I asked if that prediction was serious, the response was “it depends on how you define manufacturing.”  In today’s fact-challenged world, every word is up for redefinition.

Many of the resist talks focused on metal photoresists, either through the addition of metal to a chemically amplified resist, or the design of a metal-based resist from scratch.  The higher absorption of these resists has the potential to improve the stochastics at EUV, where photons are precious.  So far, though, chemically amplified resists still outperform any of the metal-based resists at a given dose.  Even with better absorbed photon statistics, a metal resist still must do everything else right, especially perform at high resist contrast.  Resist fundamentals do not change with material platform.

There were also many interesting DSA talks.  I especially liked the use of high-speed AFM to watch microphase separation during annealing of DSA patterns with bake time (Kenji Yoshimoto of Kyoto University).  I started off the computational lithography session with a talk on lithography stochastic fundamentals.  I didn’t write up a paper, but I’ve posted my slides here.  During that session I enjoyed listening to Sander Wuister of ASML talk about modeling metal resists.

After a wonderful conference banquet Wednesday night, Thursday began with an hour-long invited talk by Chris Williams of Virginia Tech, teaching us about additive manufacturing.  It was a great talk about a fascinating field, with a mind-boggling number of potential applications.  I was extremely interested to see many innovations from the chip packaging field (such as photosensitive polyimides) starting to influence materials research in 3D printing.

Robert Brainard updated his talk from SPIE earlier this year on double-deprotected chemically amplified resists.  The idea is to increase the deprotection reaction order from 1 to something closer to 2 in order to increase the chemical gradient after post-exposure bake.  While this could work, the stated goal of lowering roughness using a higher gradient will not work.  Roughness is proportional to noise over gradient and a higher reaction order will, at best, increase noise and gradient in direct proportion.  Added steps can only add more noise on top of what’s already there, so I think this idea can only lead to more roughness, not less.

Overall, the photopolymers conference is a great venue for talking about resist chemistry, is less commercial than the SPIE resist conference, and gave me the chance to get to know more of my Japanese resist colleagues.  I’m glad I came.

And now, a story from the “Another Reason Why I Love Japan” department.

After spending two days in Tokyo, I took a train Tuesday morning to Chiba to attend the start of the photopolymers conference.  When I went to my hotel to check in, I reached into my pocket and found nothing – my wallet was missing.  Lost?  Stolen?  I didn’t know.  But I knew I couldn’t check in or pay my conference registration fee, and that it would be a long five days in Japan without money or a credit card.  When I relayed this story to my friend Nagahara-san, he immediately said “This is Japan.  Your wallet was not stolen.  You’ve lost it, and someone will turn it in.”  Taking his advice, I asked the front desk at my hotel to call the train stations I had visited that morning.  Checking back at lunch time, my wallet was found and was at the office of the first train station I had visited that morning!  An hour and a half later, I was at the train station with my wallet in hand, missing not a single thing (including the cash)!  I love Japan.

Captive in Orlando

61st International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication
Orlando, FL, May 30 – June 2, 2017

Unlike some conferences, the 3-beams conference moves to a new location each year.  This means that some years it is in a location I like better than other years.  Last year was Pittsburg (liked it), in the past it has been in Las Vegas (didn’t like it), and this year it was in Orlando, Florida.  I like Orlando, at least when I’m with my family and we are going to Disney or Harry Potter World.  But when your conference is at a resort (Disney’s Coronado Springs, in this case) and you’re not there with family, you become trapped.  It was a 20 minute cab ride to any restaurant or bar that wasn’t part of Disney.  So I ended up eating mediocre resort food and paying $11 for a beer.  The only redeeming factor was that the conference was good.

Historically, the core of the triple beam conference has been lithography (using electrons, ions, photons, and non-beams) along with correlated disciplines (resist, etch, deposition, elf-assembly, etc.).  The application of these fabrication techniques to make devices has always been important to the conference as well.  It is not a manufacturing conference (one presenter described electron-beam lithography as a “high throughput” option for nanopatterning), but that is what I like about it.  It is quite academic, with many students giving papers (a plus for someone like me who spends more time at industry-focused conferences).  Unfortunately, this year saw a larger than normal number of visa cancelations (students who couldn’t get visas to travel here to present).

One of my favorite papers of the conference was a plenary talk by D. Frank Ogletree of Lawrence Berkeley National Labs.  As our industry barrels towards implementing UEV lithography in manufacturing, we still lack answers to very fundamental questions about the exposure mechanisms for EUV resists.  Ogletree described one way to study the complicated interactions of a high-energy photon with a resist material by interacting those photons with model compounds in the gas phase.  Simplifying the interactions allows for much more detailed measurements and easier interpretation of results.  The surprising outcome was how high-energy EUV photons could cause massive fragmentation of the resist molecules.  The full implications for resist chemistry are still unknown.

Dr. Nishikawa of the University of Tokyo gave an interesting talk on directly exposing and cutting DSA (directed self-assembly) patterns using direct-write e-beam lithography.  The results looked very promising.  My favorite student paper was by Yao Luo of Texas A&M, who is working on my favorite topic – stochastic-induced line-edge roughness.  In a technique that I have also successfully employed, she used a Monte Carlo simulator to create simulated scanning electron micrographs of simulated rough features with known statistical characteristics.  She then examined the impact on SEM noise on the ability to properly measure feature roughness.  Great work.

The multi-beam maskwriter company IMS gave an update on their tool development.  They are currently shipping a maskwriter tool with 262,144 programmable electron beams, each with 20-nm resolution capability.  This enables the printing of a state-of-the-art photomask in about 10 hours, limited mostly by the data path (275 TB of data for one mask).  This is great progress for mask making, but we all want to know, how much faster can this tool become?

There were several interesting papers on DSA (from MIT and NIST, among others), but little progress on its application to the semiconductor industry.  Carolien Boeckx of Imec discussed the healing properties of DSA for contact holes.  Unfortunately, you still can’t heal a missing contact.

I gave the last paper of the last day of the conference.  My thanks to the 25 hearty souls who persevered to the end and sat through my talk on how SEM errors influence line-edge roughness measurements.  I then made a mad rush to the airport to catch the last plane to Austin.  I needn’t have rushed.  Thanks to weather my flight was canceled and I found myself captive in Orlando for one more night.

SPIE Advanced Lithography Symposium Postscript

It is 10 days since the SPIE Advanced Lithography Symposium, and I have finally finished and submitted all my papers!  If you are interested in any of them, you can find them on the Fractilia website here:

Note that for the tutorial talk I gave I will not be preparing a paper, but you can get a copy of the slides I presented.  And for those you who didn’t attend the talk, this is the way it ended:


SPIE Advanced Lithography Symposium 2017 – day 4

In the second talk of the morning in the EUV session, Andrew Liang of Lam Research showed how much work it takes to optimize a new process, and how that work can pay off.  Local critical dimension uniformity (LCDU) is a term that refers to stochastic-induced variation in CD.  Conventionally, CDU looks at the variation of CD across a chip, exposure field, wafer, and lot caused by things like mask CD variation, film variations across the wafer, focus control across the exposure field, hotplate temperature uniformity, and many other factors.  The length scale of these variations tend to be quite large compared to the pitch of the patterns being printed, so that two feature next to each other are assumed to be largely affected in the same way by all of these variations.  Stochastic variations, on the other hand, have a length scale (called the correlation length) that is small compared to the feature size so that we can understand its impact by looking at any features, even ones right next to each other.  By measuring the CDU of a small group features (a 7X7 array of contact holes, for example) we can isolate the stochastic impact on CD uniformity from the other CDU factors.  This is the idea behind LCDU.

Liang optimized the hard mask below the resist by switching to a thinner PECVD film, optimized the lithography process to maximize the image log-slope, and optimized the etch process using atomic layer etching.  The last item is the most interesting to me, since it looks like it is possible to use an etch rate that varies as a function of aspect ratio to compensate for resist CD variation.  When the resist CD is too small, the aspect ratio of the hole is higher.  For a typical etch process, this higher aspect ratio would cause shadowing of the etchant and a reduction in etch rate, making the small hole even smaller.  But etching can also involve polymer deposition on feature sidewalls to slow etching down.  If that polymer deposition slows down with higher aspect ratio, maybe it is possible to increase the etch rate when contact holes are too small, thus improving the LCDU.  To me this seems like magic, but only in the sense of Arthur C. Clarke’s third law, “Any sufficiently advanced technology is indistinguishable from magic.”  Others have reported on this very exciting possibility, and I am looking forward to learning more.

Ravi Bonam of IBM collected a large amount of data from a programmed roughness mask, a mask that contained an added rectangle (jog) along the feature edge of varying size and frequency.  By measuring the mask and the wafer after printing, something can be learned about the optical transfer of roughness from the mask to the wafer, and the ability of wafer metrology to see roughness at specific frequencies.  Unfortunately his data analysis and presentation left me unable to grasp a single lesson learned from his data.  I’ll have to wait for the manuscript.

Tom Wallow gave a comprehensive overview of sources of metrology variation for the case of metrology used for OPC model calibration.  His two laments were the same as from every lithography model developer.  First, customers want models to fit the data better than the data uncertainty justifies.  Second, models that are based on physics require data that has accuracy, not just precision.  Historically, metrologists have focused on precision for the simple reason that accuracy is just too hard a problem to comprehend.  Tom, I hope people absorb your lessons, but don’t hold your breath.

I presented my last paper at 2pm, and then I was mostly done for the day.  After giving my last demo of Fractilia’s new MetroLER software, socializing with friends that I rarely see at other times throughout the year became my last priority of the conference.  I sampled only about 10 – 15% of the papers in the symposium, and I learned a tremendous amount from them.  I dub this year’s major theme to be stochastics, and I am glad for the attention that it is finally receiving.  I’ll go home with many ideas to investigate and try out.  For anyone interested in my papers and presentations, I’ll be posting them soon on my lithoguru website, and also on the new Fractilia website.  But first I’m going home to relax.

SPIE Advanced Lithography Symposium 2017 – day 3

It is just me or is 8:00am too early for the first technical talk of the day?  At least on Wednesday the 8:00am talk was an excellent one.  Oktay Yildirim of ASML presented a basic but very useful roughness model.  Alas, I had to run out before the end of his paper to give my own paper in the metrology session.  The problem with stochastics becoming the major theme of this year’s conference is that there have been stochastics papers everywhere, often conflicting with each other.  The morning metrology session was all roughness measurement.  Of course, I was pleased with Barton Lane’s presentation of SEM errors and their impact on roughness measurements, but since I was a coauthor that is to be expected.  I also gave my own paper on a new method for roughness characterization – the level crossing method.  I was especially impressed with Dr. Serap Savari’s work on applying modern algorithmic techniques for power spectral density (PSD) estimation.  I guess I’m going to have to figure out what a discrete prolate spheroidal sequence is.

Ravi Bonan of IBM went back to an old idea that remains underutilized today – the programed roughness mask.  Similarly, Sergey Babin of aBeam created a metrology test structure with deterministic randomness.  Please don’t ask me to explain.  The core concept of both is the same – create small structures with programmed “roughness” to test our measurement and analysis capabilities.  More creative ideas in these regards will certainly be welcome.

A creative idea came from Harm Dillen of ASML.  He used an array of very dense contact holes to measure the field distortion of scanning electron microscope images.  His application was edge placement error measurement, but as Barton Lane described earlier it also impacts roughness measurements.  Modeling the distortion using a typical first-order overlay model allows the systematic contribution (about 0.6 nm RMS for his data) to be subtracted out.  This amount of distortion is enough to have a quite noticeable on line-edge roughness measurement.  I can’t wait to try this method out.

Alex Robinson of Irresistible Materials gave a talk on increasing the sensitivity of EUV resists.  I didn’t attend.  But he did corner me later and run through it with me.  His cartoon chemistry looked very interesting – a believable mechanism for achieving second order acid amplification chemistry.  Now that such chemistry looks possible, I’ll have to think about the roughness implications more carefully.  That’s the problem with stochastics – nothing is obvious the first time you think about it.

The evening ended with another round of excellent hospitality suites (thanks to all of the companies that feed me so well throughout the week), with the PROLITH party always being my favorite.  For all of you who have asked me if my new company (Fractilia) will revive the traditional bathtub party of my old company (FINLE), the answer is no.  The bathtub party must remain the stuff of lithography legend; Fractilia will create its own traditions.

SPIE Advanced Lithography Symposium 2017 – day 0

Sunday was a beautiful day in San Jose, bright and sunny.  Just a few blocks away, though, last week’s flooding has devastated whole neighborhoods, causing possibly billions of dollars in damage and the evacuation of more than 10,000 people.  Though very close, that disaster seems far away as we begin the SPIE Advanced Lithography Symposium and shift our focus from what nature can do to us to what we can do to harness nature.

Attendance is again at about 2,200 people this year, similar to what it has been for the last eight years.  It’s hard to get a full sense of what this week will teach us, but just a cursory glance at the program reveals same major shifts in emphasis in the lithography world.  The Advanced Lithography Technologies conference, now renamed Emerging Pattern Technologies, has shrunk considerably over the last two years, from 71 orals and 27 posters in 2015, to 27 orals and 14 posters this year.  There are far fewer papers on DSA (directed self-assembly) this year, as well as fewer multibeam e-beam lithography and nanoimprint lithography papers.  DSA’s early promise of “resolution in a bottle” has given way to the hard reality of defectivity for a thermodynamically driven system.  Meanwhile, the EUV community is emphasizing their progress towards manufacturing readiness.  Some hard realities await them as well, though, and talks on line-edge roughness seem to be everywhere.

This gives me the opportunity to advertise my first talk, at 5:40pm on Monday, at the end of the first day of the EUV conference.  I have been invited to give a 40 minute tutorial talk on stochastic-induced roughness.  I believe this is the first time that we’ve had a tutorial talk at the Advanced Lithography symposium, and I am very excited to be giving it.  I hope everyone interested in line-edge roughness will endure the late hour and come and listen.

For those who are interested in the talk but can’t be at the Symposium, I’m excited about SPIE’s new program to capture each presentation on video.  SPIE will be filming the slides and recording the audio for each talk.  For presenters who have given SPIE permission, these talks will then be posted on the SPIE Digital Library as a permanent record of the presentation.  So, if you do miss my tutorial talk, look for it to show up in a few weeks on the Digital Library.

Let the Symposium begin!

SPIE Advanced Lithography Symposium 2016 – day 4

I bounced all over the conference on Thursday (the last day), from Tim Brunner’s paper predicting focus and overlay performance based on measured wafer bow and thickness, to Derk Brouns’s update on an EUV pellicle.  Nelson Felix of IBM discussed early use of EUV lithography for 10-nm and 7-nm node logic devices (as opposed to the high-k1 results reported by Intel on their 14-nm node).  The data-packed paper deserves much further study and I hope his proceedings paper contains all the information from his presentation.  He mentioned the rule of thumb, commonly discussed this week, that if EUV throughput can get above a reliable 60 wafers per hour, EUV is cost effective compared to combining three 193 immersion patterns.  All such calculations assume many things, not all of which I was able to catch from the talk, that greatly affect the outcome.  I’m sure that equal yield is assumed (a standard assumption for cost calculations), but we also need to know the dose that was assumed.  Nelson mentioned that while printing 36-nm-pitch lines and spaces, going to a dose of 35 mJ/cm2 produced a noticeable yield improvement compared to a 30 mJ/cm2 dose.  I wish that we might see more data like this in the future, since we desperately need to understand the yield/dose trade-off.

Jo Finders of ASML gave an excellent talk, emphasizing what many resist companies don’t quite get:  the quality of the image coming from the scanner matters a lot.  For decades, lithographers have focused on optimizing masks and illumination to maximize the NILS (normalized image log-slope) of the image.  Exposure latitude is proportional to NILS, so every little bit of improvement matters.  Early EUV work was at larger k1 values, and many people were not yet concerned with process windows, so NILS did not get as much attention.  But Jo reminded us of something we should never forget:  LER, LWR and the local critical dimension uniformity (LCDU) that is caused by that roughness are all inversely proportional to NILS.  Thus, for a given resist material at a given exposure dose, the easiest way to lower LER and LCDU is to increase the NILS, using classical approaches like illumination optimization.  Of course, everyone should be following Jo Finder’s advice.  We also have to be aware that any roughness measurements must be made at the same NILS to be comparable – something almost no one does.  The RLS (Resolution-LER-Sensitivity) trade-off should always be NILS corrected.  Another option is to use the LER/LWR resist metric that I proposed, though it seems not to have caught on since I published it in 2014.  Still, that metric is also NILS dependent and so NILS must be controlled in order to make comparisons.  One way to do so is to use a reference image, such as the interferometric images produced at Paul Scherrer Institut.

On another topic, ASML and Nikon described the performance of their latest 193 immersion scanners.  Overlay, focus control, and throughput on these new tools are very impressive.  Tool productivity has increased by a factor of 2 in the last 7 years or so, and I wonder where continued productivity improvements will come from.  A very difficult problem.

The last paper I attended was on detailed characterization of roughness measurements.  My friend and roughness expert Vassilios Constantoudis could not make it this year, so his co-author Hari Pathangi did a good job of delivering the paper for him.  Building on the earlier work of Ricardo Ruiz, this paper explored the correlation of roughness from feature to feature for both SAxP and DSA.  (I hope you have been reading this blog all week, because as you can see I am now dropping acronyms as if I learned them in elementary school).  For these techniques we must look not just at edge-to-edge correlations, but feature-to-feature correlations across multiple pitches.

So what are my impressions of the symposium overall?  This was a year of important but incremental progress.  Let’s look at how various technologies are trending.

Trending Up:

EUV lithography has made important progress over the last year and the mood among many is more positive (especially since two years ago).  Now that the 80W sources in the field are running in a moderately reliable fashion, learning in the fabs has begun in earnest.  ASML has demonstrated a 200W source, but the delta between lab demonstration and reliable performance in the field is a great one.  The key question for the source will be when do customers get their next upgrade?  Will it be 100W by the end of the year?

Nanoimprint lithography (NIL) has made lonely progress at Canon (since they bought Molecular Imprints) and Toshiba, with SK Hynix joining the effort to some extent.  And while serious investment in NIL came years too late, there is still a good chance they will succeed, at least for flash production.

Stochastic awareness seems to have hit critical mass this year.  At the dimensions we are now experiencing, the fundamental stochastics of the world are coming to dominate lithographic behavior.  Stochastics are hard to control, but any hope that we might do so will be through greater theoretical understanding and careful experimental measurements.

Trending Down:

Directed self-assembly (DSA) progress has been disappointing in the last year, though that could be due to my inflated expectations.  It appears that no one is yet using DSA in production, and every head-to-head with a competing method (atomic layer deposition for contact hole shrinks, SAQP for lines and spaces) has favored the incumbent process.

EUV resists switched from excitement about nanoparticle resists to excitement about metal-containing resists.  There is much hope that real progress is just around the corner, but results remain depressingly consistent:  the only way to lower LER is to raise the dose.  Resist developers have not embraced a thorough understanding of stochastics as the foundation of their resist design, and have not internalized Lord Kelvin’s dictum:  if you can’t model it, you don’t understand it.


Of course, there were many other things going on at the conference, and I was able to attend only a small fraction of the many talks presented this past week.  As always, I am invigorated by the progress and learning that I have seen, and exhausted by the non-stop intellectual challenges that this symposium provides.  When I hit that post button for this final summary, I’m going to bed.

SPIE Advanced Lithography Symposium 2016 – day 2

It is 8 am on Tuesday, and the extreme dilemma that is the SPIE AL Symposium is facing me head on.  Where do I go?  Do I go to the ASML EUV status talk?  Toshiba on the status of nanoimprint for flash manufacturing?  Ben Bunday’s review of metrology challenges at 5 nm?  Or Moshe Preil’s overview of patterning challenges below 10 nm?  Every conference scheduled one of their best talks for first thing in the morning.  I chose none of the above and went to the patterning materials conference.  What a treat!  Six papers in a row full of science, deep dives into mechanisms, data, chemical structures, new measurement approaches, attempts at theoretical explanations, and great discussions.  I saw no graphs with missing axes labels, “resist A vs. resist B” comparisons, spin, or marketing pitches.  It was what I love most about SPIE.  Congratulations to all the authors in that session (and especially the students).

I did manage to make it to a different Toshiba talk later in the morning on the status of nanoimprint lithography (NIL) development towards manufacturing readiness.  Here is the summary.  For 2x-nm flash device manufacturing (that is, devices with half-pitch 20-nm and above), defect levels have undergone continuous improvement such that they are confident that all defect specs will be met before the end of this year.  According to Toshiba, the only thing prevent NIL from going into manufacturing at these nodes is throughput, which is off by around a factor of 2.  Another talk by Canon explained their roadmap for achieving the desired throughput (at least 50-60 wafers per hour for the four-head cluster tool) in the next year by decreasing resist spread time.  NIL is extremely close to a go at that node.

But the value of NIL is not at the 2x-nm flash nodes, where it replaces a mature SADP process.  Instead, it is at the 1x-nm node, where it can replace the more expensive and problematic SAQP.  There, much more work needs to be done.  Defect levels are much too high, both on the as-manufactured templates and during wafer processing.  Progress is also being made here, but two-three more years will be required at the least, I suspect.

I enjoyed a presentation by Gian Lorusso of Imec on attempts to validate LER/LWR metrology accuracy.  What I got out of the talk was basically this:  it is really, really hard.  We know about the many problems of LER measurements using SEMs, but measurements using TEM or AFM are even worse.  Today, we have no alternative but to use our top-down SEM, which means we need to be much more careful about characterizing biases in those measurements and analyzing the data in the most rigorous way possible.

(An aside to all users of LER metrology:  you haven’t measured LER or LWR until you report not just sigma, but the correlation length and roughness exponent as well.  You have no excuse – just do it.)

By the end of a long day I participated in a panel discussion celebrating the 30-year history of the metrology conference.  I have a simple rule for evening panel discussions:  if they are not fun, don’t bother.  This one was fun – thank you Ofer Adan.  The champagne helped as well.  Next week, I’ll try to post my 7-minute talk on the philosophy of metrology.

As a final note for day two, I’ve had a number of people ask me if my skeptical attitude towards the ultimate manufacturing success of EUV lithography has changed.  There has been good progress made in the last year.  The 80W tools in the field have finally become reliable enough to allow engineering development.  Everyone is talking about ASML’s 200W demonstration.  These are all impressive achievements.  But my skepticism remains.  Source power in the field is still just 80W (will we exceed 100W by the end of the year?).  Throughput in the field is enough to peel another layer of the onion and find several more problems with EUV (see yesterday’s post).  And there are many more onion layers to go, with problems as yet undiscovered.  All of these things take time, and time is the enemy of EUV lithography.  EUV has missed the 10-nm node at all companies, and will almost surely miss the 7-nm node at all companies as well.  Will it be ready for the 5-nm node?  A 5-nm node that must be relaxed to accommodate the resolution limits of single patterning EUVL?  Will any fab be able to make money at 5 nm, with or without EUV?  My skepticism remains.