Solar Panels, Year 3

Here is another annual update on my solar production and electricity consumption. In late January, 2017, I turned on my new solar panels. I have 30 panels, 320 W each, for a total capacity of 9.6 kW (LG320 NeON2 MonoX Plus panels with microedge converters). In the first year I generated 96% of the electricity I consumed (a magical year, with near perfect weather – sunny, but not too hot). The second year was not as good since my consumption went up 6% and my generation was down 10%. The result was that my panels generated 81% of my usage for the second year. The third year is off a little more. My consumption when up 1.5%, and my generation was down 5% compared to the second year. The final result is that the panels generated 76% of my usage in the third year. The weather is the biggest variable, and I need to find an authority that measures the amount of sunshine in Austin so that I can try and determine if there are any other factors than that at play.

A lithography casualty

The canceling of conferences has become an inevitable consequence of the COVID-19 pandemic.  Today the first lithography conference took a hit.  The 64th International Conference on Electron, Ion, And Photon Beam Technology and Nanofabrication (EIPBN, also known as three-beams or triple beam), scheduled for the end of May in New Orleans, has been cancelled.  I’ve enjoyed this conference many times in past years, and I look forward to attending again in the future.

COVID-19: the data

Like almost everyone else, I am now hunkering down in my house doing the “social distancing” thing. Since the announcement of the first confirmed coronavirus cases in Austin Thursday night (less than four days ago), events have been accelerating almost as fast as the virus has been spreading. My kids are on Spring break, but I doubt they will be going back to school next week. The supermarket shelves are getting bare. I work from home anyway, so that is no change for me.

Like everyone else, I am consuming the news about the spread of this disease. But as a data geek, I want more than what you find in the newspapers (yes, I’m old school – news is something you read, not something you watch). The first obvious place to go is the CDC website. Their data is perhaps the most trustworthy, but also conservative and a few days old. There is also the more accessible Worldometers site, with very up-to-date numbers that may be less reliable than the CDC (though I am not diving into that). Below are a couple of links and graphs from those sites. The bottom line: the number of cases in the US seems to be doubling every four days. That’s a 10X increase every two weeks. Exponentials – yikes. If we don’t flatten this curve, that will mean 400,000 cases in a month, and the entire country in two months. It is time for us to flatten the curve.

https://www.worldometers.info/coronavirus/country/us/

https://www.cdc.gov/coronavirus/2019-ncov/cases-updates/world-map.html

World map showing countries with COVID-19 cases

(Countries with coronavirus cases shown in green, as of March 14.)

SPIE Advanced Lithography Symposium 2020 – day 4

The final day of the conference!  Zhingang Wang of Hitachi talked about CD-SEM tool matching, describing all of the sources of variation that affect matching.  This year he added a new error source to his list:  detection/image level variation.  The variation of SEM image quality across the SEM image field is something that I have been discussing (related to Fractilia) for the past few years, and I am glad to see Hitachi start talking about it as well.

Jara Garcia Santaclara gets my vote for best paper title of the conference – “One metric to rule them all:  new k4 definition for photoresist characterization”.  I’m a sucker for Lord of the Rings references.  Jara and Bernd Geh have made some good progress on the k4 factor introduced by Bernd last year (essentially trying to create a predictive scaling relationship that is more detailed than Gregg Gallatin’s original RLS formulation).  Their work seems to be converging with my (still unfinished) approach to simple LER modeling that I discussed at the last two EUVL Symposiums.  With some more effort, we all might get these scaling rules to a very useful place, so I hope we continue to work this topic.

There were several useful papers on measuring and modeling secondary electron blur radius in EUV resists, an important but difficult topic.  But most of the Thursday papers were not as on-target to my interests as the earlier days.  I did end the day with a fun paper on “Sub-Wavelength Holographic Lithography” (SWHL) by a Swiss startup of that name.  Holographic lithography is an old approach with many very interesting characteristics (no projection lens, masks that are hard to make but insensitive to defects).  There were other attempts to make this approach work 15 years ago and 25 years ago, but improvements in lasers, mask making, and computational capabilities seem to be enabling a renewed interest.  I’ll be watching Nanotech SWHL to see how they do.

Looking back over the week I have two closing thoughts.  This is, I believe, the first time I have been to SPIE Advanced Lithography without seeing Grant Willson, who retired last year.  I saw him present at my first SPIE in 1985, met him at my second conference in 1986, and have been friends with him ever since.  I’m glad he is enjoying his retirement, but we certainly miss him here.  The week has also seen an escalating concern over the new coronavirus, COVID-19.  Like everyone else I am monitoring developments with morbid fascination, but also to see how it will impact my immediate future.  And it has.  If there is any positive to the spreading fear over the spreading virus, it is that I will soon be traveling far less.  I have started asking customers if we could schedule our meetings, demos, and courses using video conferencing rather than in-person, and they are readily agreeing.  Maybe such accommodations will be a permanent trend, with the significant savings in time and resources that come with less travel (not to mention a better quality of life when I spend more time with my family).  I will look to this thought as a small consolation.

SPIE Advanced Lithography Symposium 2020 – day 3

Ron Schuurhuis of ASML began the day with a review of the improvements they have made to the NXE:3400C, many of them (such as inline tin refill and reduced collector swap times) resulting in fairly significant tool productivity enhancements.  But something else in his presentation has encouraged me to go off on a rant:  calculated throughputs based on unrealistic resist sensitivity assumptions.  In the very early days of EUV, throughput calculations were based on the mythical 5mJ/cm2 (dose-to-size) resist.  After source power increased by something like an order of magnitude, a mythical 10mJ/cm2 resist was introduced for theoretical throughput calculations.  As the source power increased further, ASML grudgingly acknowledged that these unrealistic dose targets would never be met and allowed the theoretical dose for throughput calculations to rise again (to 15 and then 20 mJ/cm2), but always climbing more slowly than source power so that they could still claim a rising throughput.  In the Schuurhuis presentation I saw what appeared to be the next transition, to a 30mJ/cm2 mythical resist.  (As an example, their calculated 170 wafer per hour throughput using a 20 mJ/cm2 resist becomes 135 wph assuming a 30 mJ/cm2 dose-to-size.)  Assuming 30 mJ/cm2 is certainly better than assuming 20, but line/space patterning requires closer to 40 mJ/cm2 at modest pitches (and higher for smaller pitches), and contact holes need over 50mJ/cm2 (to print, for example, 40nmx70nm pitch staggered arrays).  Can we just admit reality for once and start using 40 mJ/cm2 for all future throughput calculations on the 0.33 NA tool?

I was excited by a talk by Rich Wise of Lam Research showing extremely preliminary results for a dry deposited, dry developed metal-organic nanocluster resist.  These early results looked promising.  I always worry that nanocluster resists will not have high enough development contrast (best measured using a focus-exposure process window and mask linearity compared to a standard resist), but I look forward to seeing more from Lam on this material in the future.

Gurpreet Singh of Intel gave a pair of talks on complementing EUV with directed self-assembly (DSA).  (I have to be careful with my spelling – I started to say that DSA was “complimenting” EUV, but in fact the opposite is true).  The first application of DSA was in rectification:  print lousy EUV patterns at a tight pitch (say, 30 nm or 28 nm) and low dose, etch them into an underlayer, then fix the terribly rough features using DSA guided by the underlayer pattern, without pitch division.  This works very well for line/space patterning and could replace an SAQP flow, but of course Intel said nothing about design rule constraints.  Their goal was clear:  improve edge placement error by reducing the pitch walking endemic to SADP and SAQP.  With the low EUV doses possible using this approach, it might even be cost effective.  They used the very mature PS-b-PMMA system since it has the possibility of sufficiently low defectivity for practical manufacturing.  But pushing to smaller pitches (below about 24 nm) will likely require a new material, and he proposed the development of a “modified” PS-b-PMMA system as the best path forward.

From Charlie Liu of IBM I heard my new acronym of the week:  PB&S (print big and shrink).

Hyo Seon Suh of imec updated us on their continuing progress in making DSA practical for high-volume manufacturing (full disclosure – I was a coauthor on this talk).  Through a number of optimizations they were able to shrink the unbiased LER from 3.0 nm to 2.5 nm, while keeping defectivity near the 2/cm2 level.

Customer meetings kept me away from much of the afternoon talks, and as a substitute for the canceled KLA PROLITH party many of us met up in the evening at my new favorite San Jose brewpub, Uproar, where we toasted another successful day advancing lithography.

SPIE Advanced Lithography Symposium 2020 – day 2

Tuesday was a heavy day of stochastics for me.  Greg Wallraff of IBM got me off to a good start with his interesting simplified Monte Carlo-like stochastic resist model.  As expected for chemically amplified resists, higher PAG loading had a big effect on reducing stochastic variability, and higher amounts of photodecomposable quencher had a smaller but noticeable impact.  Also as I expected, acid amplifiers only make things worse stochastically.  All of his simulations used a 15nmx15nmx15nm voxel, but I hope he will look into the impact of voxel size on his simulation results.  I think that understanding the role of the averaging volume (voxel size essentially) is one of the biggest gaps in our knowledge of stochastic behavior.

Andy Neureuther gave a fantastic talk on the role of dissolution path in determining missing contact defectivity.  His algebraic model looked very insightful, and dissolution path plays an underappreciated role in how photon shot noise manifests itself in stochastic defectivity of contacts.  Dario Goldfarb of IBM and Patrick Theofanis of Intel each showed wonderfully rigorous experimental and simulation studies (respectively) of EUV resist exposure mechanisms.

Peter de Bisschop of imec once again provided the incentive (and the data) for the industry to look more closely at EUV defectivity versus dose, this time by adding pitch variation and challenging us to model the results.  Both Synopsis and Mentor used that same dataset to develop models for stochastic defectivity (a work still in progress).

I gave my paper for the week (comparing the noise sensitivity of different CD-SEM edge detection algorithms), as did two of my coauthors on separate studies.  Jen Church of IBM compared LER with defectivity for lines and spaces and LCDU with defectivity for contacts.  While she showed that unbiased LER and low-noise LCDU were required, these metrics alone were not enough to predict defectivity or yield.  Charlotte Cutler of DuPont gave the third in a series of papers she has presented at the Patterning Materials conference on using power spectral density (PSD) analysis for resist design.  In my completely biased perspective, both of these papers were highlights of the day.

At the metrology conference I enjoyed a talk by the National Metrology Institute of Japan on using AFM as a roughness reference metrology, even though I disagree with some of their conclusions.  Comparing SEM and AFM measurement of the same sample (an etched silicon line), the two measured edges matched extremely well except at the high frequencies.  The authors attributed these differences to SEM noise, but failed to recognize the role of instrument resolution.  With an uncharacterized tip size of about 7nm, their AFM is a much lower resolution instruments (in terms of high-frequency roughness measurement) and so was unable to see the high frequency variations that are visible in a SEM (admittedly contaminated by SEM noise).  I hope the authors will continue their work be comparing AFM to unbiased SEM measurements, and that they will work to deconvolve the tip shape from the AFM measurements (hopefully using different tips with different shapes).

The final talk I heard was a fantastic one, by Luc Van Kessel, a student at the Technical University of Delft.  He studied a subject I have long been fascinated with:  how does the 2D surface roughness of the sidewall of a feature translate into the 1D edge roughness observed in a top-down CD-SEM?  For his 300V SEM simulations, the observed top-down edge an isolated line was essentially the extreme X-Y points of the 3D feature.  Things were a bit more complicated for a small space because of the aspect ratio making the bottom of the space less visible in the SEM.  Also, his 500V simulations were only preliminary and could be somewhat different due to the greater penetration distance of those higher-energy electrons.  Great work, Luc!

With Harry Levinson, I ended the day by hosting an all-conference panel called “A toast to lithography’s past:  what we learned from technologies not used in HVM”.  Hans Loschner gave us the history of the life (and death) of ion-beam projection lithography, Reiner Garreis of Zeiss discussed 157-nm lithography, Alexander Liddle recalled his time working on Scalpel, and I filled in for Tobey Aubrey (who couldn’t make it) to talk about our lessons learned from proximity x-ray lithography.  While I enjoyed all of the discussion, I didn’t enjoy the unfortunate logistics.  We made the big mistake of scheduling our panel immediately after the EUV retrospective panel.  Not only was the EUV panel late to finish (as expected for EUV), but the time to transition between panels was far too short.  The topics of the two panels were very similar, but nobody would want to sit through four hours of panel discussions at one time.  Lessons learned not only about lithography, but about panel discussions as well.

SPIE Advanced Lithography Symposium 2020 – day 1

The plenary session began with opening remarks and awards.  We welcomed two new Fellows of SPIE:  Hiroshi Fukuda and Mike Rieger.  Congratulations for that well-deserved recognition.  This year’s Frits Zernike Award for Microlithography was given to Winfried Kaiser of Zeiss for his major contributions to 193nm and EUV optics.  He also gets my nomination for most dapper Zernike award winner!  Three good plenary talks (on machine learning, in-memory computing, and Flash memory process technology) were full of interesting technical information (so long as you ignored the commercial embedded in the Kioxia talk).

The opening keynote talk for the EUV conference was given by Charlie Wallace of Intel, where he described not just the current status of EUV lithography for manufacturing 32 nm pitch lines and spaces, but the immense challenges of shrinking the pitch to 30 nm or 28 nm.  As pitch shrinks, higher doses are required, but even at these high doses defect rates are too high.  Some quotes:  “It is execution time for EUV lithography.”  “We need fundamental improvement in EUV materials”.  “Improvement in metrology is required.” 

A quick pause to talk about Intel.  Anyone who has read this blog over the last several years knows that I have complained about the paucity of semiconductor-maker talks at this and other lithography conferences, and especially about how few talks Intel would give.  I must now recognize that this criticism belongs to the past.  Intel has really stepped up their game recently, and they have seven presentations at AL this year.  Thank you, Intel!  The entire lithography community appreciates your contribution.

The Metrology conference opened with an interesting experiment – the first keynote was given remotely.  Alain Diebold of SUNY Polytechnique called in and spoke while his slides were advanced onsite.  While not ideal, it was much better than a cancelled talk and I appreciate the conference chairs thinking experimentally about how to let the talk go on.  Several afternoon talks covered the important topic of edge placement errors and how to characterize them using contour-based metrology rather than the traditional CD-based measurements.  It is clear that this approach is quickly becoming a standard method.  In the EUV session, Marie Krysak of Intel showed again how standard “three-sigma” characterization of stochastic contact hole variations was not good enough to predict chip yield.  She used a combination of non-Gaussian extrapolation and stress tests (underexposing to make the defect rates high enough to measure), both of which produced similar results when comparing the performance of different EUV resists.

Some news:  Canon and (at the very last minute) Qoniac have cancelled their hospitality events.  I still managed to stay out too late and drink too much beer (thank you Fractilia and Inpria).

SPIE Advanced Lithography Symposium 2020 – day 0

For me Sunday is always about teaching.  I’ve been teaching at the start of this conference every year since 1990 (except the year I was too sick to leave my hotel room – a rotavirus as it turns out).  Alas, my good friend and co-instructor John Petersen was unable to attend the conference at the last minute (responsibilities for his new AttoLab at imec have intervened), so I reverted to my old ways of teaching 8 hours by myself.  That is definitely a young person’s calling, though I survived with my feet a little tired and my voice mostly intact.  My course’s attendance was about the same as last year, but the biggest course, Introduction to Microlithography, had only about 50% of the registered students show up.

Early indications are that conference attendance will be down about 15% (300 people) compared to last year, with about half of that drop coming from Asia and most of the other half from Intel (only authors and conference chairs have been allowed to come from Intel).  I found out that another large company has canceled their hospitality suite – ASML.  That leaves a few resist companies, Qoniac, Mentor Graphics, and of course Fractilia carrying on with their evening events (I’m probably missing some in this list).  That is definitely enough to have fun every night of the week. 

As I await the beginning of the conference, I am anticipating a few things.  Developments in Directed Self Assembly (DSA) have been somewhat muted here the last few years, giving conference attendees the possible impression that interest has been waning.  But rumors are spreading that several companies are on the verge of high-volume manufacturing with DSA.  The quiet seems to be due to commercialization, not lack of interest.  I’m not sure that we’ll hear more about those plans this week, but I’ll listening for them.

Finally, I have realized that my personal transition is complete.  I no longer call myself a lithographer.  I am a metrologist, and I am proud of it.  My conference of focus will be the metrology conference, and I find everything about metrology incredibly interesting!  I still know how to think like a lithographer, and I still work hard to adopt a stochastic mindset – metrologists must steep themselves in the technology of what they measure.  I’ll be following the stochastic conference track wherever it leads me, knowing that without good metrology none of us will have the data needed to make good decisions.

SPIE Advanced Lithography Symposium 2020 – prologue

The SPIE Advanced Lithography conference begins with one word on everyone’s mind:  coronavirus.  I am fairly certain that the actual impact of coronavirus on the conference will be zero, but the impact of fear of the coronavirus is large.  Many Asian companies have either decided not to send anyone, or are sending very few people.  From Taiwan, I have heard that Winbond is the only semiconductor company sending people.  From Korea, Samsung is sending maybe only one person.  Last week Intel decided to dramatically reduce the number of people they are sending.  This has a snowball effect, as many vendors seeing that their customers will not be there are also reducing their presence.  On Sunday, KLA and Nikon both canceled their major events (the KLA Litho Users Forum and the Nikon LithoVison).  Several (but not all) Sunday technical meetings have also been canceled.  Most of the big companies have canceled their hospitality suites (KLA, TEL, Hitachi, Applied Materials).  Of course, health concerns are the stated reason for the cancellations, but I think cold, hard cash is the real reason.  Why spend a huge amount of money on an event when hardly any of your customers are going to be there?  Not to worry – Fractilia’s Happy Hour will go on as planned!

As the week goes on, I’m sure we’ll all understand better how the coronavirus scare will impact the technical events, especially cancelled papers.  As for SPIE, every event of the conference will go on as planned.  While the conference may be smaller than expected, I am still expecting it to be a good one.

MNE 2019

I have a confession to make.  Sometimes I choose to go to a conference mostly based on its location.  My core conference is SPIE’s Advanced Lithography, and I would go to that wherever it was (San Jose is nice, but it is not a “destination”).  But there are a number of conferences at the periphery of lithography, and in particular conferences that touch on lithography for the academic community.  Three conferences that fit this bill are the Electron, Ion, and Photon Beam Technology and Nanofabrication conference (EIPBN, often called 3-beams or triple beam) in the US, Microprocesses and Nanotechnology Conference (MNC) in Asia, and Micro and Nano Engineering (MNE) in Europe (thought of as sister conferences).  They can be interesting, informative, thought provoking, and even inspiring.  But often there is little of direct relevance to my current focus.  In other words, I don’t need to go, but sometimes I want to go.  How much I want to go depends on where it is.

This year, the MNE conference was on the island of Rhodes, Greece, and guess what?  I wanted to go.

These three conferences, EIPBN, MNC, and MNE, used to have a lot more lithography content, much of which was relevant to semiconductor lithography.  Today, however, semiconductor lithography has priced itself out of the academic market, and universities employee either vastly outdated lithographies, or high-resolution approaches that are so slow they could never be considered for the semiconductor industry.  Still, it is always nice to find out what the academic research community is up to in the world of lithography.

But frankly, for me, it is generally not worth traveling half-way around to world to go to one of these conferences.  Unless I want to.

And so I found myself this week in Rhodes, Greece, listening to interesting papers, presenting one myself, and enjoying the amazing beauty and heritage of the one of the Greek islands.

The MNE conference is extremely vibrant, with a lot packed into three days:  150 orals, 360 posters, and four evenings of social activities.  Student participation is huge (often the point of an academic conference), and as an old, cynical industry guy, it is refreshing to be around enthusiastic young people.

The plenary session started with an old friend – Yan Borodovsky, retired from Intel, who talked about Moore’s Law: Past, Present, and Future.  As he told me after, “I can’t believe I am still being asked to speak when in my 5th year of retirement!”  For a retired guy, he gave a great talk.  His “past” described the three pillars of microelectronics:  Von Neumann’s computer architecture of CPU, memory, and I/O, Moore’s Law of reducing transistor costs, and Dennard scaling that makes a transistor better when it is smaller.  One by one these pillars of microelectronics are falling away.  Dennard scaling ended in the mid-2000s when voltage scaling became increasingly difficult.  Smaller transistors are no longer better, we just hope they are not terribly worse.  Moore’s Law has dramatically slowed of late, and Yan made a bold prediction – the end of reduced cost per transistor would occur in 2021, coinciding with the attempt to bring EUV lithography into high volume (really high volume) manufacturing.  The last pillar, Von Neumann’s architecture, is the hardest to escape given its phenomenal success.  But current high-performance computing is limited both by the speed and power consumption associated with transferring data back and forth from memory to CPU.  New architectures, such as neuromorphic computing, could redefine these limits.

Yan’s main point was that lithography choices have always been based on the constraints of these three pillars.  He added one further important constraint:  that today’s logic chips (such as CPUs, GPUs, and Application Processors) are seriously defect intolerant.  One defect (for example, one missing contact hole) will kill an entire chip.  This reality rules out any lithography approach with defect densities greater than about 0.1 defect/cm^2.  That’s a shame, since lithographies such as directed self-assembly (DSA) and nanoimprint lithography (NIL) are high resolution and cheap, but don’t have the defect densities required for today’s logic devices.  A change to a computing architecture that is fundamentally defect tolerant would enable lower-cost lithography choices.  Since today’s chips have 50% or more of their cost coming from lithography, the impact would be huge.  It was clear that Yan is hoping for a defect-tolerant future, so that lower-cost lithography approaches become practical.  As am I.

There were only a few other talks specifically relevant to semiconductor folks like me.  B.T. Chan of imec talked about the etch challenges that come with making FinFETs with only one or two fins.  Michal Danek of Lam Research talked about atomic layer deposition and atomic layer etching as enablers to 3D NAND devices.

The social interactions of the conference were some of the highlights for me.  The reception Monday night before the start of the conference brought us to crusader-era architecture (the Knights of Saint John ruled the island from about 1300 to about 1500) in the old town of Rodos (Rhodes).  It was lovely, and included Homeric singing (what a treat).  Tuesday night was a beach party (we could see Turkey from the beach).  Wednesday night was the conference reception, and I had the honor of serving as a judge for the very popular Micrograph contest.  John Randall began the micrograph competition at the 3-beams conference in 1995, and he brought it to MNE in 2005.  This year there were over 60 entries, and the judging was hard.  You can find this year’s micrographs at https://www.zyvexlabs.com/contests/2019-3/.

The conference ended Thursday night with a bus trip to Lindos, an ancient and beautiful city.  A fitting end to a conference defined, for me, by its location.

Musings of a Gentleman Scientist