My hat is off to the speakers who brave the 8am time slot on the last day of the conference.  They are often talking to a sparse crowd as the stragglers slowly trickle in.  The exception was William Miller of Qualcomm, whose excellent talk at 8am was very well attended.  For us semiconductor types, it was very enlightening to hear the customer’s perspective on what goes wrong in manufacturing.

Since my papers were all done for the week, I spent the day just listening.  Bruno Azeredo (ASU) gave a fascinating talk on electrochemical nanoimprinting of silicon in the newly revamped Novel Patterning Technologies conference.  I also enjoyed watching my former student Meghali Chopra present results on etch optimization with software from her new company Sandbox Semiconductor.  My coauthor from imec Vito Rutigliani gave a great talk, showing how different underlayers (below the resist) affect the image contrast of SEM images, changing the noise and bias in roughness measurements so that biased roughness measurements are essentially useless.

There were several talks aimed at using defect review SEMs as fast metrology tools, allowing for a dramatic increase in the amount of data that can be practically collected.  This is great for looking for stochastic defects, especially defective contact holes that occur at or below the ppm level (one bad contact hole in a million).  We still need to see calibration results comparing these larger pixel size/larger spot size tools to traditional CD-SEMs.

The stochastics theme continued on Thursday with afternoon talks by Peter de Schepper of Inpria and Eric Hendrickx (standing in for Peter de Bisschop) of imec looking for defects at the million-feature level.  Another talk in the EUV Resist Roughness session set me off on mini-diatribe, which I will repeat here for those who didn’t watch me coopt an author’s Q&A time to give it the first time. 

In trying to understand how low we might be able to push line-edge roughness, we often want to understand the separate contributions of photon shot noise and resist noise (both of which are translated by the image log-slope into the observed edge errors).  Suppose the total 3-sigma roughness for our features is 3nm, and we estimate that this same resist exposed with an image that has no photon shot noise would produce 1.8 nm of roughness.  Would it be appropriate to say that the resist contributes 60% of the total roughness?  No, and making such a statement is quite misleading.  Why?  If the photon shot noise and the resist contributions to roughness are independent, then their contributions would add in quadrature, so that variance (not standard deviation) is divided up between the two sources.  If we took out the 1.8 nm resist contribution, what would the roughness be?  2.4 nm, only a 20% reduction from the original 3nm, not a 60% reduction.   If we insist on assigning a percent contribution to photon and resist noise, we must do it on the variance scale.  In this case, photon shot noise would contribute 64% to the total variance, and the resist would contribute the other 36%.  When it comes to noise, we should always focus on the biggest contributor since the quadrature addition will amplify its importance.

I stayed till the bitter end, closing out another great week at the SPIE Advanced Lithography Symposium.  We didn’t get much of an update from ASML or the semiconductor companies on the recent progress of EUV lithography.  Multibeam electron lithography and directed self-assembly continue to make slower than expected progress in wafer patterning.  But multi-beam mask writing is doing great, enabling very good progress in nanoimprint lithography.  The hot topics wax and wane from year to year, but progress is always made, thanks to the innovative work of the people at this conference.  See you next year!

The theme of this year’s SPIE Advanced Lithography Symposium may be stochastics, but the buzzphrase of the year is definitely machine learning.  I counted 11 papers with that phrase in the title, not to mention one short course, two full sessions on the topic, and numerous mentions in other talks trying to boost their “cool” factor.  I am happy to say I did not attend any of these papers.

I’m just now learning about a technique that I believe TEL introduced last year to help with the edge placement error problem of complementary lithography (which I often misspell as “complimentary”, though this approach is anything but free).  In complementary lithography long lines and spaces are patterned in one lithography/etch step (SADP, for example) and then cut up into smaller segments using a second litho/etch step.  Sometimes the cuts are so challenging that two or more cut patterning steps are required to make one final pattern.  This is where edge placement error (EPE, though more correctly described as edge-to-edge overlay error) comes in.  Each cut patterning step will have an overlay error relative to the other cut patterning steps and relative to the lines and spaces being cut.  If the cut’s overlay error perpendicular to the line is too large, it could accidentally cut a neighboring line.  For this reason the cuts are made short, becoming almost contact holes.  It would be easier to pattern the cuts if they were rectangular shaped (long dimension perpendicular to the lines), but then we have these potential overlay problems.

This is where the “multi-color” SAxP approach comes in.  If you make every other line in your long line/space pattern out of a different material, and those materials have different etch rates, it is possible to cut one line in an etch process without worrying whether the neighboring line is damaged by a misplaced cut pattern.  Alas, this technique comes with increased processing steps (and cost) to create the “colors” (the lines of different material), but it is probably worth it if it enables easier lithography of the cuts.

Wednesday was the day when life as a working stiff got in the way of pretending I was still a Gentleman Scientist.  I missed a large chunk of papers in the middle of the day due to customer meetings.  Time is the only truly limited resource.

For me the highlight of the day, if not the week, was the special session on shot noise in the EUV conference.  2018 is the 100-year anniversary of the seminal paper by Walter Schottky where he coined the phrase “shot effect” and described the statistical properties of a then newly discovered noise in low-current vacuum tubes due to the discrete nature of electrical change.  Since shot noise has become an integral part of our community’s vocabulary recently, I suggested to Ken Goldberg and Felix Nelson that they organize this special section in honor of this anniversary.  I gave a tutorial talk on the history of shot noise, then Patrick Naulleau and Robert Brainard followed with two great talks on the topic.  I loved the session, especially since I got to give a talk with no technical content (my favorite kind of talk).  If you missed it, remember that SPIE is now recording the talks and will post them on the SPIE digital library in the coming weeks (for those authors who have given permission).

The poster session afforded me the opportunity to engage in one of my favorite conference activities – talking with Vassilios Constantoudis.  It was enlightening and educational as always.

The late nights are starting to catch up with me, and Wednesday always makes things worse because of the KLA-Tencor party.  There are always too many good friends there to catch up with.  Still, I think I will be able to make an 8am talk on Thursday.  I hope.

Midway through the week, my first impressions have solidified into a clear view of the conference themes.  I think we can call this the year of stochastics.  Five years ago it was hard to get anyone to listen when you talked about stochastic effects in lithography, but today it seems to be the only thing people are talking about.  What has changed?  EUV lithography is close enough to reality that people can imagine, and even visualize, using EUV to make something other than test images for their SPIE paper.  We can visualize making devices, devices that must yield.  And it is not a pretty picture.  For years we talked about progress in all the other areas of EUV lithography, with a parting comment that “EUV resists must improve” to fix the stochastic effects.  But now it is clear that we must attempt to make devices with the resists we have today, and no miracles are on the horizon.

The other thing that has changed is the shift in emphasis from stochastic-induced roughness to stochastic-induced defects.  It is hard for us lithographers to understand how an extra nanometer of linewidth roughness might affect our devices, but it easy for us to understand the implications of a missing contact hole.

I started my day in the Metrology conference with a session dedicated to LER/LWR measurement.  Gian Lorusso introduced the “imec protocol”, his attempt to standardize the measurement of roughness (full disclosure:  I was a coauthor).  He began by describing an exercise imec performed where they sent a set of identical wafers to 13 companies and asked them to measure the linewidth roughness and send back the results.  The answers he received varied by +/- 30%.  The need for standardization in measurement is obvious.  The main problem is bias in the measurements due to SEM noise (and how that bias varies with measurement conditions), so the most important recommendation is to always use unbiased measurements.  He also described how the ITRS recommended measurement approach has become outdated with today’s low correlation length processes:  a 2-micron line length is no longer needed.  Gian’s paper is extremely important, and I hope that the imec protocol is widely followed from now on.

My first paper of the conference was in this same session, which included simulation results that were finished the night before (cutting things just a little too close!).

It may seem like I am pitching too many papers that I was a co-author on, but I am going to do it anyway.  Charlotte Cutler of Dow gave an excellent talk on her use of power spectral density analysis to improve resist materials.  As a resist maker, Dow regularly measures features after the lithography step (in industry jargon, ADI:  after develop inspect), but has little access to after-etch results since those depend heavily on each customer’s etch process.  But when it comes to roughness, it is the after-etch performance that matters.  So, Charlotte needs to correlate her ADI measurements to after-etch results.  Traditionally, that has meant looking at the ADI 3-sigma roughness with the assumption that a low ADI 3-sigma roughness would translate into a low after-etch 3-sigma roughness.  Alas, it often does not.  To explore why, she created two matrices of resist formulations and measured the power spectral densities of the roughness of each of them.  She found that while after-develop 3-sigma roughness was not a good predictor of after-etch 3-sigma roughness, the after-develop unbiased PSD(0) was.  I predicted last year that this approach would work (in my EUVL Symposium paper), and it is very gratifying to see this prediction proved out experimentally.

There seem to be fewer ASML papers at the conference this year (is it my imagination?), but I did catch Jan von Schoot talking about their plans for a high-NA EUV scanner.  Every time I see drawing of this tool, or pictures of the lens manufacturing facility under construction at Zeiss, I am amazed at how massive and complicated this tool will be.  Perhaps it is designed to make the NXE:3400 seem only moderately complex.

I walked around the poster session (much smaller than in years past), and saw quite a few good ones.  The conference is now half-way over, but I won’t say it is a downhill ride from here.  Wednesday will be exciting!

The plenary session Monday morning began with awards.  We recognized four new SPIE fellows from our community:  Jason Cain, Alexander Starikov, Peter Trefonas, and Reinhard Voekel.  Congratulations!  We had no presentation of the SPIE Frits Zernike Award for Microlithography this year, for a very sad reason.  Just before the award committee was to vote on the winner, one of the nominees for the award, Nick Cobb, died.  (I’m on that committee.)  So instead of making a Frits Zernike award this year, we decided to honor Nick with a special mention and the establishment of the Nick Cobb Memorial Scholarship (thanks to the generation contribution of Mentor Graphics and a matching contribution by SPIE).  It was very touching to see Nick’s family there for this special recognition.

The three plenary talks were all interesting, and each as different from the other as they could be.  Yan Borodovsky came out of retirement to discuss his views on the biggest challenges still facing EUV lithography as it nears high volume manufacturing (HVM).  I liked this quote about EUV:  “It’s not about if, or even when, but how well?”  Yan focused on the quality problems of EUV in two major areas.  First, the EUV mask is a complex phase shifting mask with unintended phase shifts.  Controlling and managing these phase shifts is critical and difficult.  Second, stochastic defects “must be eliminated for EUV HVM” according to Yan.  How to do this in the short term is unclear, but since these stochastic failures increase dramatically as feature size decreases, the long-term solution is even more problematic.  Yan suggested that the only practical approach is to live with them by moving our logic computing devices to some type of fault-tolerant architecture, such a neuromorphic computing or fine-grained cores (thousands of small cores, so that if one or a few go bad you still have a valuable chip).  I’m not sure how long it will take to move away from the standard Von Neumann computing architecture, but it won’t happen in the next few years, that is sure.

Dan Hutcheson gave his typically upbeat assessment of the future of Moore’s Law – somehow the community will overcome the technical hurdles because the economic incentives to do so as so compelling.  But of course, this will not be true forever.  Dan’s opinion was that trying to predict when the end might come would be self-defeating by reducing one’s motivation to forestall that end.  I don’t agree, but I understand his point.

While Dan’s talk gave a 40,000-foot view of the economics of lithography, Stephen Hsu’s plenary talk dove into the gory details of OPC and RET (resolution enhancement technology) from ASML’s perspective.  The many innovative technologies developed by ASML to improve NILS (normalized image log-slope, a measure of aerial image quality) will result in reduction in stochastic problems, but it is clear that this will not be enough.  Thus, Stephen reminded us that “more resist improvement is needed for EUV.”  To that I counter that more improvement in the EUV source is in fact what is needed, and no call to improve resists should be unaccompanied by a call to improve source power.

George Gomba gave the first keynote address of the EUV conference and he made the same mistake as Stephen Hsu:  admitting that EUV photon shot noise was a big problem and then calling on resist improvements as the required solution.  In then end, however, he accurately described the three major unsolved problems in EUV as stochastic failures, mask defectivity, and meeting the source power roadmap going forward.

Following George was the second keynote by Chris Ober of Cornell, talking about his group’s approach to developing EUV resists.  Unfortunately, in a parallel conference Geert Vandenberghe of imec was also giving a review of the status of EUV resists.  The lack of coordination between parallel sessions in different conferences is a perennial complaint of mine.

In the afternoon I attended the joint EUV and resist session.  I have to admit a great thrill at seeing Fractilia’s roughness measurement product, MetroLER, used so effectively in nearly all of the papers in that session.  TEL and imec gave four of the five talks in the session, and both are users of MetroLER.  Thus, my view of those papers is quite biased, unlike their measurements, which were quite unbiased.  (Sorry, LER measurement nerd humor). 

The 6pm conference welcome reception was very nice – I liked it being held in an open area of the conventional hall floor rather than in a room, and I like the beer that was available.    After many good conversations at several different hospitality suites, it was back to my room to prepare for my first talk, early the next morning.

Sunday is, for most attendees of the Advanced Lithography Symposium, a travel day to get to San Jose, or just a normal Sunday for those who are local.  But it is technically the Symposium’s first day.  For me it was a 14 hour day, beginning with teaching an all-day short course (with John Petersen), giving two talks at different company-sponsored workshops, and ending with a planning dinner for next year’s conference.  Let’s just say I’m all warmed up and ready for the papers to begin!

2018 will be a very important year in the development of EUV lithography towards high-volume manufacturing (HVM).  (I’m pretty sure I say this every year.)  ASML now says that it’s NXE:3400 will be the tool that is capable of HVM, and the first 3400 was shipped and installed at Samsung the end of last year.  Will we see some early results from this tool?  I’m not holding my breath.

Attendance this year will be similar to that of the last 10 years, in the 2000-2200 range.  But abstract submittals were down 11% from last year.  That disconnect (still strong attendance but reduced author participation) is probably a result of the continuing industry consolidation.  In particular, the semiconductor makers are shrinking to a “big three” plus a few others.  But the real problem is that the big three are not pulling their weight as authors.  Intel is giving exactly zero papers at the symposium this year.  Zero. TSMC is the primary author on three papers.  Samsung is primary author on 10 papers (getting more respectable).  Filling the void left by the big three are GlobalFoundries (with nearly 40 papers) and imec (I didn’t even try to count).  It’s time for Intel and TSMC to step up and become more enlightened: contributing to the advancement of the lithography community as a whole is good for the whole industry, including them.

OK, I’ve had my first rant.  I guess that means the conference has officially begun.

Just over one year ago I launched, with Ed Charrier, our new company, Fractilia.  After inventing a new concept for detecting edges in a noisy SEM image, we released last July the first version of our flagship product, MetroLER, for measuring the roughness of line/space patterns.  Last week we released a second version of MetroLER, including the measurement of contact holes.  It has been a very busy year.  Alas, I have had the give up my title as Gentleman Scientist – I have a real job now!

But old habits die hard, and the mindset of the Gentleman Scientist is not easily revoked.  As we approach this years’ SPIE Advanced Lithography Symposium, I will attempt to wear two hats (and titles).  As CTO of a start-up, I will be meeting with customers, giving papers showing results from our product, and evangelizing about the right way to measure pattern roughness and stochastic effects in lithography.  But as a lingering Gentleman Scientist I will also try to appraise the state of lithography in our industry.  I’ll watch a small subset of the many presentations given over the next week and let you know in these posts what I think.  I’ll see old friends, have interesting hallway conversations, and drink too much every night.  As always, I will learn a tremendous amount and have a great time doing it.

I’ll also experience a fair amount of cognitive dissonance as this skeptic of EUV lithography works hard to make EUV lithography a success.  If EUV lithography cannot attain long-term commercial viability I don’t want it to be due to poor pattern roughness measurement!  Like everyone else, I’m looking forward to hearing about all the latest developments in EUV, but also in the many other subjects that bring us lithographers together.

So look out San Jose, here come the lithographers!

43^rd International Conference on Micro and Nanoengineering (MNE 2017)
September 18-22, 2017, Braga, Portugal

I love port.  The fortified wine is lovely before or after dinner, and makes me feel more sophisticated and refined than I deserve.  Port is made exclusively in the Duoro Valley of northeastern Portugal, then aged in wooden barrels in the coastal city of Porto.  I’ve always wanted to visit there, so when I discovered that the 2017 MNE (Micro and Nanoengineering) conference was being held in Portugal, I made a plan to attend.

I’ve been to MNE twice before, in Leuven and Grenoble, but that was many years ago.  This conference is much like the 3-beams (EIPBN) conference in the US, or the MNC (microprocess and nanotechnology conference) in Asia:  academic, nanotechnology oriented, with some lithography content (though diminishing over the years).  The timing of the conference was good this year, because I was just finishing up a joint project with Gian Lorusso and his team at imec (Belgium) and we needed a venue to publish our work.  MNE fit the bill.

The conference was held in the small northern town of Braga, chosen because it is home to the brand new International Iberian Nanotechnology Lab (INL), where the conference was held.  With about 800 people in attendance (and 535 oral and poster papers), it is a vibrant and growing conference.  So much so that the MNE community has decided to create a new professional society to manage itself.  This was announced for the first time at the conference, and I’m not sure any of us know what that means.

I thought that two of the best talks were the two opening plenary talks.  The first, by Frank Schuurmans, was on the history of ASML plus a discussion of EUV (extreme ultraviolet) lithography.  There was nothing new there for me, but it was good for this academic audience to see what could happen when the multibillion-dollar might of the corporate world is applied to a difficult technical problem.  Olivier Joubert is an academic with a foot in industry, working at CEA-Leti but heavily involved with Applied Materials.  His plenary talk on trends in plasma etching was definitely the best plasma etch talk I’ve ever heard.  The two big drivers for etch technology today are Flash, requiring very high ion energy to dig deep holes, and FinFETs, requiring very low ion energy to prevent damage.  The third driver is the growing list materials that need to be etched.  He discussed line-edge roughness (my favorite topic), proposing that UV light from the plasma is the main cause of the smoothing that occurs during etch.  He also said “There are very few places in the world where you can accurately measure linewidth roughness.”

The plenary talks were held at the elegant and historic Theatro Circo in downtown Braga, and between the two talks was an “artistic performance.”  The performance was modern dance (some of it in cleanroom bunny suits), music incorporating sounds recorded at INL, and a surrealistic video based on scanning electron microscope images.  It sounds weird, but it was fantastic!  The group of performers worked with the INL “artist in residence”, a position as valuable as it is unexpected.  I hope more organizations follow what I hope will be a trend and establish artist in residence programs.

That afternoon Victor Blanco of imec gave a keynote talk “EUV insertion at the N5 node”.  It was the same talk I had heard the week before from Greg McIntyre at the EUVL Symposium in Monterey, but it was great for this audience to hear what the semiconductor industry is doing and what our challenges are.

On Wednesday I enjoyed a talk by Lars-Erik Wernerson of Lund University, Sweden, on progress towards vertical nanowire transistors using alternate channel materials.  It is good to see progress being made on what I suspect will be the future transistor architecture of mainstream logic devices.  Naomi Halas of Rice University gave a fabulous talk on the use of metallic nanoparticles for various sustainability initiatives.  Her talk made clear how many amazingly interesting and important projects can make use of nanofabrication (not just boring old semiconductors).

The conference banquet on Wednesday night was held in a port wine cellar in Porto, with my first (but not last) exposure to the port wine making process.  It was a great dinner, but in the tradition of the region finished very late into the night.  It was hard to get up for the first talks the next morning.

On Thursday I enjoyed a talk by Mark Schvartzman on nanodumbbells (if you’re curious, look them up).  Thursday also had a few interesting metrology papers, but overall the overlap between the content of the conference and my interests was not terribly large.  I gave my paper as a poster on Tuesday, and by Thursday I was saturated with as much nanotechnology as I could absorb.  I decided to play hooky on Friday, skipping the conference in favor of visiting Porto.  I got to downtown about noon and went straight to the port cellars.  Seven hours, five cellars, and 27 tastings of port later I declared the last day of the conference a success.