The week of SPIE’s Advanced Lithography Symposium is finally in the past, and life is beginning to settle down towards normal again.  As always, I have collected up the week’s worth of blog posts and put them on my conferences web page.  You can find my summaries of 20 different lithography conferences going back to 2006 here:

http://www.lithoguru.com/scientist/conferences.html

I bounced all over the conference on Thursday (the last day), from Tim Brunner’s paper predicting focus and overlay performance based on measured wafer bow and thickness, to Derk Brouns’s update on an EUV pellicle.  Nelson Felix of IBM discussed early use of EUV lithography for 10-nm and 7-nm node logic devices (as opposed to the high-k1 results reported by Intel on their 14-nm node).  The data-packed paper deserves much further study and I hope his proceedings paper contains all the information from his presentation.  He mentioned the rule of thumb, commonly discussed this week, that if EUV throughput can get above a reliable 60 wafers per hour, EUV is cost effective compared to combining three 193 immersion patterns.  All such calculations assume many things, not all of which I was able to catch from the talk, that greatly affect the outcome.  I’m sure that equal yield is assumed (a standard assumption for cost calculations), but we also need to know the dose that was assumed.  Nelson mentioned that while printing 36-nm-pitch lines and spaces, going to a dose of 35 mJ/cm2 produced a noticeable yield improvement compared to a 30 mJ/cm2 dose.  I wish that we might see more data like this in the future, since we desperately need to understand the yield/dose trade-off.

Jo Finders of ASML gave an excellent talk, emphasizing what many resist companies don’t quite get:  the quality of the image coming from the scanner matters a lot.  For decades, lithographers have focused on optimizing masks and illumination to maximize the NILS (normalized image log-slope) of the image.  Exposure latitude is proportional to NILS, so every little bit of improvement matters.  Early EUV work was at larger k1 values, and many people were not yet concerned with process windows, so NILS did not get as much attention.  But Jo reminded us of something we should never forget:  LER, LWR and the local critical dimension uniformity (LCDU) that is caused by that roughness are all inversely proportional to NILS.  Thus, for a given resist material at a given exposure dose, the easiest way to lower LER and LCDU is to increase the NILS, using classical approaches like illumination optimization.  Of course, everyone should be following Jo Finder’s advice.  We also have to be aware that any roughness measurements must be made at the same NILS to be comparable – something almost no one does.  The RLS (Resolution-LER-Sensitivity) trade-off should always be NILS corrected.  Another option is to use the LER/LWR resist metric that I proposed, though it seems not to have caught on since I published it in 2014.  Still, that metric is also NILS dependent and so NILS must be controlled in order to make comparisons.  One way to do so is to use a reference image, such as the interferometric images produced at Paul Scherrer Institut.

On another topic, ASML and Nikon described the performance of their latest 193 immersion scanners.  Overlay, focus control, and throughput on these new tools are very impressive.  Tool productivity has increased by a factor of 2 in the last 7 years or so, and I wonder where continued productivity improvements will come from.  A very difficult problem.

The last paper I attended was on detailed characterization of roughness measurements.  My friend and roughness expert Vassilios Constantoudis could not make it this year, so his co-author Hari Pathangi did a good job of delivering the paper for him.  Building on the earlier work of Ricardo Ruiz, this paper explored the correlation of roughness from feature to feature for both SAxP and DSA.  (I hope you have been reading this blog all week, because as you can see I am now dropping acronyms as if I learned them in elementary school).  For these techniques we must look not just at edge-to-edge correlations, but feature-to-feature correlations across multiple pitches.

So what are my impressions of the symposium overall?  This was a year of important but incremental progress.  Let’s look at how various technologies are trending.

Trending Up:

EUV lithography has made important progress over the last year and the mood among many is more positive (especially since two years ago).  Now that the 80W sources in the field are running in a moderately reliable fashion, learning in the fabs has begun in earnest.  ASML has demonstrated a 200W source, but the delta between lab demonstration and reliable performance in the field is a great one.  The key question for the source will be when do customers get their next upgrade?  Will it be 100W by the end of the year?

Nanoimprint lithography (NIL) has made lonely progress at Canon (since they bought Molecular Imprints) and Toshiba, with SK Hynix joining the effort to some extent.  And while serious investment in NIL came years too late, there is still a good chance they will succeed, at least for flash production.

Stochastic awareness seems to have hit critical mass this year.  At the dimensions we are now experiencing, the fundamental stochastics of the world are coming to dominate lithographic behavior.  Stochastics are hard to control, but any hope that we might do so will be through greater theoretical understanding and careful experimental measurements.

Trending Down:

Directed self-assembly (DSA) progress has been disappointing in the last year, though that could be due to my inflated expectations.  It appears that no one is yet using DSA in production, and every head-to-head with a competing method (atomic layer deposition for contact hole shrinks, SAQP for lines and spaces) has favored the incumbent process.

EUV resists switched from excitement about nanoparticle resists to excitement about metal-containing resists.  There is much hope that real progress is just around the corner, but results remain depressingly consistent:  the only way to lower LER is to raise the dose.  Resist developers have not embraced a thorough understanding of stochastics as the foundation of their resist design, and have not internalized Lord Kelvin’s dictum:  if you can’t model it, you don’t understand it.

Of course, there were many other things going on at the conference, and I was able to attend only a small fraction of the many talks presented this past week.  As always, I am invigorated by the progress and learning that I have seen, and exhausted by the non-stop intellectual challenges that this symposium provides.  When I hit that post button for this final summary, I’m going to bed.

It is 8 am on Tuesday, and the extreme dilemma that is the SPIE AL Symposium is facing me head on.  Where do I go?  Do I go to the ASML EUV status talk?  Toshiba on the status of nanoimprint for flash manufacturing?  Ben Bunday’s review of metrology challenges at 5 nm?  Or Moshe Preil’s overview of patterning challenges below 10 nm?  Every conference scheduled one of their best talks for first thing in the morning.  I chose none of the above and went to the patterning materials conference.  What a treat!  Six papers in a row full of science, deep dives into mechanisms, data, chemical structures, new measurement approaches, attempts at theoretical explanations, and great discussions.  I saw no graphs with missing axes labels, “resist A vs. resist B” comparisons, spin, or marketing pitches.  It was what I love most about SPIE.  Congratulations to all the authors in that session (and especially the students).

I did manage to make it to a different Toshiba talk later in the morning on the status of nanoimprint lithography (NIL) development towards manufacturing readiness.  Here is the summary.  For 2x-nm flash device manufacturing (that is, devices with half-pitch 20-nm and above), defect levels have undergone continuous improvement such that they are confident that all defect specs will be met before the end of this year.  According to Toshiba, the only thing prevent NIL from going into manufacturing at these nodes is throughput, which is off by around a factor of 2.  Another talk by Canon explained their roadmap for achieving the desired throughput (at least 50-60 wafers per hour for the four-head cluster tool) in the next year by decreasing resist spread time.  NIL is extremely close to a go at that node.

But the value of NIL is not at the 2x-nm flash nodes, where it replaces a mature SADP process.  Instead, it is at the 1x-nm node, where it can replace the more expensive and problematic SAQP.  There, much more work needs to be done.  Defect levels are much too high, both on the as-manufactured templates and during wafer processing.  Progress is also being made here, but two-three more years will be required at the least, I suspect.

I enjoyed a presentation by Gian Lorusso of Imec on attempts to validate LER/LWR metrology accuracy.  What I got out of the talk was basically this:  it is really, really hard.  We know about the many problems of LER measurements using SEMs, but measurements using TEM or AFM are even worse.  Today, we have no alternative but to use our top-down SEM, which means we need to be much more careful about characterizing biases in those measurements and analyzing the data in the most rigorous way possible.

(An aside to all users of LER metrology:  you haven’t measured LER or LWR until you report not just sigma, but the correlation length and roughness exponent as well.  You have no excuse – just do it.)

By the end of a long day I participated in a panel discussion celebrating the 30-year history of the metrology conference.  I have a simple rule for evening panel discussions:  if they are not fun, don’t bother.  This one was fun – thank you Ofer Adan.  The champagne helped as well.  Next week, I’ll try to post my 7-minute talk on the philosophy of metrology.

As a final note for day two, I’ve had a number of people ask me if my skeptical attitude towards the ultimate manufacturing success of EUV lithography has changed.  There has been good progress made in the last year.  The 80W tools in the field have finally become reliable enough to allow engineering development.  Everyone is talking about ASML’s 200W demonstration.  These are all impressive achievements.  But my skepticism remains.  Source power in the field is still just 80W (will we exceed 100W by the end of the year?).  Throughput in the field is enough to peel another layer of the onion and find several more problems with EUV (see yesterday’s post).  And there are many more onion layers to go, with problems as yet undiscovered.  All of these things take time, and time is the enemy of EUV lithography.  EUV has missed the 10-nm node at all companies, and will almost surely miss the 7-nm node at all companies as well.  Will it be ready for the 5-nm node?  A 5-nm node that must be relaxed to accommodate the resolution limits of single patterning EUVL?  Will any fab be able to make money at 5 nm, with or without EUV?  My skepticism remains.

At 8 am on Monday, the conference begins with opening remarks and the plenary session.

Bill Arnold and Harry Levinson won a “Special Contribution Award to the Art and Science of Lithography” for their two-part paper “Focus: the Critical Parameter for Submicron Lithography” published in 1988.  I read and cited those papers frequently over the years, and I still recall the clarity of their arguments and the insightfulness of their approach.  Without a doubt, these were milestone papers in the development of modern microlithography thought and practice.

Dr.  Andreas Erdmann of the Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB (Germany) became our newest fellow.  Kurt Ronse of Imec was also promoted to that rank, but he was unable to attend the symposium this year and will receive his recognition at a later conference.

The symposium awards were completed when Yan Borodovsky, recently retired from Intel, become the 13^th Frits Zernike Award winner.  Congratulations to all of them!

Some years, the plenary speakers are chosen from outside the lithography community to bring perspective and breadth to the opening of the symposium.  This year, we heard from three of our own.  Harry Levinson of GlobalFoundries gave an historical perspective on research and developments in lithography.  He mentioned the low uptime (60-70%) of early excimer lasers and the immaturity of deep-UV resists (especially sensitivity to airborne contaminants) as motivations for the extension of i-line lithography in the early 1990s.  The obvious analogy to EUV lithography was left unstated.  Two good quotes from Harry’s talk:

“Computer programming became a required skill for leading-edge lithography” (discussing the importance of computational lithography).

“Issues at the molecular scale will need to be addressed to realize the optical resolution “entitlement” of EUV lithography.”

Richard Gottscho, EVP of Lam Research, discussed deposition and etching and how those technologies will evolve to improve control in the age of multiple patterning.  In particular, the move towards atomic layer deposition (ALD) and now atomic layer etching (ALE) are greatly improving uniformity and control, though at the cost of processing speed.  These processes work by saturating the wafer with a monolayer of reactive species, which then is reacted to produce the deposition or etching.  This saturation is self-limiting and so removes many process variables from being significant factors in the process rate, easing both the process development and process control burdens.

Tony Yen of TSMC gave a very nice historical perspective on the development of EUV, one that he believes has put EUV lithography on the “eve of manufacturing”.  The very first demonstration of EUV lithography (called soft x-ray lithography until 1993) was by Hiroo Kinoshita in 1986, followed soon by Obert Wood and his many collaborators at AT&T Bell Labs.  Significant government and industry funding began in 1992 and the EUV LLC was formed in 1997 to pool the growing industry and government efforts in EUV.  With the completion of an important prototype tool, the 0.1 NA Engineering Test Stand, development work on the exposure tool shifted to ASML.  They produced their alpha-demo tool (ADT) in 2006, the NXE:3100 in 2011, and shipped the NXE:3300 in 2013.  Tony finished his historical description by saying that their first NXE:3350 has recently arrived at the TSMC loading dock.

As for the current status of EUV lithography at TSMC, Tony confirmed that the plan of record is to exercise EUV at the 7-nm node and use it in production at the 5-nm node.  The remaining problems include mask blank defectivity (currently about 20/blank, too high to use for metal patterning, but maybe OK for contact holes) and the still unproven pellicle solution.  Resist sensitivity in now closer to an acceptable range (between 25 and 30 mJ/cm2 for lines and spaces and between 35 and 40 for contact holes), but with unacceptably high linewidth roughness (LWR).

The invited talks at the EUV lithography conference gave some further perspective from Intel and Samsung on the readiness of EUV for high volume manufacturing (HVM).  Apparently, one of the big issues last year was the reliability of the tin droplet generator, part of the EUV light source.  Both Intel and Samsung were very pleased about progress on that front, so that source reliability has reached 70%, enough to do real engineering work with the tools, though not enough for manufacturing.  Intel reported end-of-line yield loss due to particles added to the mask during use.  They saw an average of one killer defect added per 20 reticle-stage-load cycles, a level that makes manufacturing impossible without a pellicle.

Seong-Sue Kim also reported on the mixed successes and failures of EUV at Samsung in the last year.  They reported 3 particle adders on the mask for every 10,000 wafers printed, a number too high by an order of magnitude at least.  But more disturbing was his report of mask damage after 40,000 wafer exposures using the 80W source.  Blisters formed within the mask multilayer, some of which popped.  Not only was the mask ruined, but contamination travelled through the optical system and made its way to the wafer.  I worry that such chemical reactions induced by the energetic photons of EUV light will behave nonlinearly with intensity.  How bad will this become when using a 250W source?

On the resist front, everyone is talking about metal oxide resists for EUV.  For many years now, Inpria has used metal oxides as an EUV resist that could deliver high resolution and low LWR, but at doses of 80 mJ/cm2 – too high to be practical given the realities of low EUV source power.  The push to get sensitivities of these resists into the 30 mJ/cm2 range has now been successful but, surprise!, the LWR is much worse.  It seems that all attempts to defy the laws of physics through chemistry continue to be unsuccessful.  Yet, since we do not have a complete understanding of all aspects of LER formation, the physical limits of roughness are unknown.  If other problems can be solved, metal oxide resists may be the way to go.

Indulge me, if you will, on another rant.  Thirty years ago I would come to this conference and see papers by resist companies that all had a familiar pattern:  here is our new material, here is a cartoon of the mechanism of why it will work, and here are one or two SEM images of high resolution patterns.  Success is then claimed.  What we learned painfully over time is that high resolution demonstrations of a material are a necessary but not sufficient condition of success.  The reason is the simple fact that a very good aerial image can produce a decent image in a mediocre resist.  The projected image maters!  So how do you know if your material is any good?  You have to consider the development contrast of the resist and how it affects process latitude.  A high image contrast can produce a good single image in a low contrast resist, but cannot produce good exposure latitude.  One needs to compare exposure latitude (or better yet, the focus-exposure process window – see the mention of the Arnold and Levinson papers above) to the entitlement process latitude (that which could be obtained from an ideal, infinite contrast resist), or at least to the current resist of record.  This lesson was learned and over the next 20 years resist contrast was systematically raised until it become sufficiently high.  Today, we almost take high resist contrast for granted (at 193 immersion, at least).

It seems that this lesson has been forgotten.  Have we experienced high-contrast resists for so long that we have forgotten how a low-contrast resist behaves?  Have we forgotten how to measure or characterize resist contrast?  I almost never see a process window for an EUV resist.  I never see a comparison of the exposure latitude to the NILS (or the best exposure latitude possible).  People compare resists printed at different numerical apertures without considering the differences in the aerial images that exposure them, or don’t even mention the conditions at which the patterns were imaged, as if a 20-nm pattern is a function of the resist alone.  We need high sensitivity EUV resists.  We need low LWR.  But we also need high resist contrast.  Let’s start measuring and reporting that, please.

One of my favorite quotes of the day: “I never thought they would discover gravity waves before EUV made it into manufacturing.”  – Kenneth Goldberg (Note:  over $1B was spent over 40 years on the gravity wave effort.)

And my favorite mixed metaphor: “We have only scratched the tip of the iceberg.” – Alex Vaglio Pret