One of the most consistent features of the long development path of EUV lithography from research towards manufacturing has been delay, especially when it comes to meeting source power and throughput milestones. Source power roadmaps have always resembled the classic marketing hockey stick graph: progress may be slow now, but it is about to take off! When questions arose about whether such dramatic improvements (always scheduled for next year) were reasonable, we began to see the roadmaps shown on a semi-logarithmic scale. Past progress now seems steeper; future requirements look less dramatic.

Last year ASML took a different tact, eschewing source power as a metric of progress towards the goal EUV manufacturing and instead focusing on tool throughput. After all, it is throughput that matters. And of course this is correct, but the change in units makes comparison of current performance to past predictions just that much more difficult. No longer is a 100 W source promised for the end of the year; instead we’ll have a throughput 70 wafers per hour by the end of 2014 and 125 wph in 2015.

At the end of 2013 these goals, 70 wph in 2014 and 125 wph in 2015, were still the official line at ASML. But now we have another unit change. Today, current performance of the EUV production tool, the NXE:3300, is described as 100 wafers per day, and the new goal is to reach 500 wafers per day by the end of 2014.

What’s going on here? When I hear a throughput spec for a manufacturing tool quoted in wafers per hour, I expect that tool to be able to operate for more than one hour. I expect it to operate all day. Sure, tool availability will always be less than 100%, and it is very important to know what that tool availability is. In that sense, wafers per day actually is a better metric to judge manufacturing readiness (or maybe it should be wafers per week). But let’s do the math here. A throughput of 500 wafers per day is an average of 21 wafers per hour. That’s a far cry from the 70 wph promised just a few months ago. In fact, 70 wph translates to 500 wafers per day if you assume only 30% availability for the tool. That’s low even by EUV standards.

So what has ASML done? They have delayed their roadmap. And to make the delay less obvious, they have changed the units. There will be much weaseling, no doubt. Was the promise of 70 wph really a promise to demonstrate the “capability” of 70 wph by the end of 2014? What does it mean to demonstrate the capability of a given throughput number anyway?

Ultimately, ASML must demonstrate the practical use of their tools in manufacturing at a throughput that lowers the cost per die compared to alternate lithography approaches, such as double or triple patterning. No hiding behind unit changes or ambiguous phrases can help them there. But between now and then the semiconductor manufacturers must maintain sufficient faith that ASML will meet that goal and do so on a schedule that enables planning of future fabs and future processes. And it is this faith that ASML is desperate to keep in place.

The last day of this symposium always seems to go by in a bit of a fog. After four days of 7 am to 10 pm (or later) nonstop lithography (and beer), the adrenaline begins to wear off. I was able to muster sufficient focus in the morning, but by lunch on Thursday I was done. To all those worthy lithographers who presented no doubt important work on Thursday afternoon, I am sorry. Next year I will try to pace myself better (or maybe the conference gods will punish me by giving me a late-Thursday speaking spot).

Thursday began with the traditional ASML review of progress on their latest EUV platform. Rudy Peeters gave the 8:00 am talk and it is clear that he has been reading my blog. He presented a modified version of a slide on a MOPA prepulse source 6 hour stability test that David Brandt presented on Tuesday, but instead of saying “printed five wafers with 99.9% yield” the slide carefully explained the simulated nature of the test and the meaning of the results. The unitless y-axis of the plot was now replaced by a relative scale (% dose error) with real numbers, though nowhere did he actually mention the power of the source (was it 10W? 20W? 30W?) and the data occupied an incredibly small fraction of the +/-4% y-axis range so that nothing more than a rough appreciation for the results could be gained.

But enough on graphs that are not intended to inform. On many fronts there was steady progress reported on the NXE:3300 platform. Jan Mulkens’ talk on mix-and-match overlay between EUV and 193i tools was especially impressive. There is still much uncertainty on whether an EUV pellicle will ever be practical, but recent progress has been good. But meaningful progress remains limited by the failure to meet each year’s updated source power roadmap. Despite obvious delays in rolling out a 30W MOPA prepulse source for NXE:3300s in the field, Rudy Peeters ended his talk with his prediction: “We’ll show 250W next year.” I look forward to seeing that milestone met, but will be more impressed when customers are shooting wafers with a 250W source.

And so another SPIE Advanced Lithography Symposium ends. I go home to Austin a little wiser and a little wearier. I was glad to meet so many young, eager scientists and engineers this year, soaking up knowledge and experience, finding sparks and catching fire. The future belongs to you.

Wednesday continued with many more papers on directed self-assembly (DSA). I’m excited about the potential for DSA, but is it bad for me to admit that my eyes started to glaze over after so many images of lines too small to see? I enjoyed an SKHynix paper on “pattern wiggle metrology”, a topic similar to things discussed by Ricardo Ruiz yesterday. Isn’t it interesting that a new idea is often discussed for the first time by several different groups simultaneously? Science and business both cherish their myths of the lone discoverer or inventor, but the reality is that we are a part of a community and have more in common than in difference.

In the Alternative Litho conference I saw an update from Mapper (very little progress) and REBL (making some progress, but not enough to catch up), as well as a little data on nanoimprint as applied to flash memory (we’ll probably have to wait until next year to find out how that work is really going).

The exposure mechanism for EUV resists is a fascinating topic. Greg Denbeaux described an apparatus he is building to expose resist to 80 eV (and eventually lower energy) electrons to explore the fundamental impact of low-energy secondary electrons on acid generation. Fascinating work – we need these kinds of fundamental studies if we ever hope to understand and optimize these resists.

And finally, a small crowd of people gathered before the still closed doors of the poster session just before 6pm in a solemn ceremony marking the official death of Moore’s Law. Despite the presence of counter protesters from the Intel religious faction, the crowd raised their drink tickets to make a virtual toast: “Moore’s Law is dead. Long live Moore’s Law.” Thus, as the poster session doors were opened, the first EOML day ended as all such future celebrations should, with technical discussions on lithography.

http://www.youtube.com/watch?v=IBrEx-FINEI&feature=youtu.be

Each year Cymer gives a talk providing an update on progress on their EUV source, and this year David Brandt’s talk was on Tuesday morning. I have never been so shocked and disappointed at an SPIE presentation in my entire career. It was a mass of inaccuracies surrounded by obfuscation and wrapped in misleading statements. I am not as adept at penetrating the techno-marketing fog as the EUV customers are (who were collectively groaning during Brandt’s talk), but let me try my best to translate a few of the statements made into plain English.

The TSMC MOPA source going down was planned. This directly contradicts what Jack Chen of TSMC said yesterday, so I don’t know how to translate this one.
Multiple MOPA sources have been installed at customer locations. Installed does not mean actual wafers have been exposed.
70W has been demonstrated. Under unstated laboratory conditions, 70W was demonstrated for 6 minutes (one graph had an x-axis with the source operating time in seconds!)
A MOPA source printed five wafers at 99.9% yield. No actual wafers were harmed in this experiment. A source was run on a lab bench and its output measured. Then, using a software algorithm, the pulses were grouped into the assumed number of pulses each die would receive, and if no pulse in that group deviated in power more than the spec allowed, that die was said to yield.
A graph shows 6 hours of controlled-loop operation of a MOPA source, but without numbers on the “power output” y-axis. This graph says nothing.
We are committed to 70 wph by the end of 2014. Using ASML’s standard calculations 70 wafers per hour translates into about 100W at the intermediate focus. Thus, this statement is essentially 100W by the end of the year, similar to what Brandt said last year and the year before. While the conditions of delivering 100W remains unstated, what it certainly does not mean is the use of a 100W source integrated onto an NXE:3300 scanner at a customer site to print wafers by the end of the year.

The statement that ASML is committed is undoubtedly true. Many, many smart, hardworking, and dedicated scientists, engineers, and staff at Cymer and ASML are doing all they can to make EUV a success. David Brandt’s talk did each of these worthy folk a great disservice.

But on to the rest of the conference. I greatly enjoyed the two sessions dedicated to “SEM Simulation and Emulation”. We have had the theoretical understanding and the tools to do a much better job of extracting information from an SEM image for a long time. It is great to see a larger effort by our community to actually making that happen. I think it is possible to look at a top-down SEM image of a set of features and extract quantitatively useful information about the line-edge roughness. Maybe one day soon we will actually do this.

My favorite talk of the conference so far was given by Ricardo Ruiz of HGST entitled “Directed self-assembly: Where does the roughness come from?” It was a model of how good data and good theoretical and mathematical understanding can be combined using clear thinking to make a difficult topic not just understandable, but easily so. (Full discloser: I visited Ricardo four weeks ago and he gave me an extended version of this talk, so the mass of data he showed was probably easier for me to grasp than most). We should all strive for such a result in our presentations.

The number of directed self-assembly (DSA) talks this year is way up (I think more than double the number from last year). Progress seems to have been remarkably fast, even though the industry has not yet converged on the one or few best options for first implementation. I’m looking forward to even more DSA talks tomorrow.

The day ended for me with Will Conley and Kafai Lai’s panel on “The Battle for the 7nm Node”. Generally, evening panel discussions are a disappointing experience. Panelist break the slide count rules and try to pack an entire talk into their allotted 5 minutes, producing a mass of uncoordinated statements that make audience participation and panelist discussions nearly impossible. Not this time. The theme was fun (a jury trial, accusing each of the technical options for 7nm node lithography of being exceptionally unpleasant, which of course they are), the panelists were highly entertaining (at 9pm, it is better to be funny than data dense), and I may even have learned a thing or two. All were good. Chris Bencher rocks.

At the plenary session, it was great to see Mordy Rothschild of MIT Lincoln Labs win this year’s Frits Zernike award. Mordy and his team (he was keen to ensure that his entire team was recognized as well) made early and critical contributions to almost every element of 193-nm lithography development, including the development, with SVG Lithography, of the first full-field 193-nm scanner in 1994. (In fact, Mordy told me that his principle contact at SVG Lithography was Frits Zernike, Jr.) After 193-nm lithography went mainstream he and his team worked on 157-nm lithography. They also made the first demonstration of immersion lithography at 157-nm, and at 193-nm, validating Burn Lin’s ideas. It is ironic that these demonstrations eventually lead to the death of 157-nm lithography. But that is the way of science and technology development: good ideas are cannibalized by better ideas.

Frank Abboud became our community’s latest SPIE fellow. Congratulations to Frank, but shame on the rest of us not nominating more of our worthy colleagues.

Bill Arnold, outgoing president of SPIE and a lithographer who has attended even more Advanced Lithography conferences than I have, gave the first plenary. I enjoyed learning more about SPIE, and seeing the pictures of Bill’s year travel the world to meet many of the 18,000 SPIE members.

Joe Sawicki of Mentor Graphics gave a nice talk on the intersection of electronic design automation and lithography (or should I say, the many intersections). He gave me my first favorite quote of the conference: “Systematic defects often start off hiding as random defects.”

The final plenary presentation was the excellent talk by Dr. Akihisa Sekiguchi of Tokyo Electron Ltd on Integrated Patterning Solutions. I enjoyed the content, style, and tone of the talk. He stated the obvious, but something that we lithographers need to hear more often: Lithography-enabled scaling came to an end a few years back. Today, scaling is patterning-driven. He showed how low 193-nm linewidth roughness (LWR) has become (less than 2 nm, though I don’t trust anyone’s numbers ever since I began studying LWR metrology). He also gave a hint of an important result we should expect to see more of during the week: directed self-assembly (DSA) defect density has decreased by a factor of 100 in the last year. Wow. The tone of Sekiguchi-san’s talk was appropriately Zen-like, a lesson most lithographers should take note of during such chaotic times. I’m glad I chose to attend his talk instead of the Dali Lama’s, who was speaking at the same time in the next town over.

The technical session began in earnest with a bevy of invited speakers (alas, I could attend only one). I went to see Jack Chen of TSMC give a refreshingly honest update of the progress and challenges of moving extreme ultraviolet (EUV) lithography towards manufacturing. Although he said the “we still have a dream to simplify the process using a small wavelength”, he made it clear that the “expensive and large program” of EUV is behind schedule. Their first NXE:3300 was installed late last year using an older source. Afeter insuring that the scanner itself was working properly, they began the upgrade process to a MOPA + prepulse source, with a “target” source power of 80 W, though the initial install will give them only 30W at intermediate focus. The tool is still down and so have not yet printed any wafers using the new source. Chen also exhibited a little frustration with source power roadmaps, showing that the promise “we’ll have 100 Watts in 1-2 years” has been given every year for over 10 years.

The second important aspect of Chen’s talk was on mask defectivity. He showed that multilayer defects on the mask cannot be repaired, so that the only choice is to get mask blank defect levels below 20 defects/blank. We are not there yet. More importantly, “fall-on adder defects” have not been eliminated. Using a mask in the EUV scanner results in defects added to the mask over time. Chen did not seem confident that these defects could be eliminated, and said that a pellicle was needed.

Mark Phillips of Intel then gave a talk about the possibility of using EUV lithography as the cut lithography tool in a complimentary lithography scheme. I liked his statement (again obvious, but something we need to hear) that reduced LWR during EUV lithography must come from higher source power, not a “miracle resist”.

In the afternoon I was intrigued by a talk by A. Oshima of Osaka University showing a positron spectroscopy technique that could measure free volume in a resist. I hope to see much more measurements from this technique in future papers. And finally two talks, by Jim Thackeray of Dow and Peter de Bisschop of Imec, showed how much we still don’t understand about pattern failure caused by stochastic effects (that is, extreme LWR). Both pointed to the development step as needing more fundamental understanding – a conclusion I wholeheartedly endorse.

I was glad to be feeling better today after feeling so miserable the day before. Still, I was not able to fully enjoy the evening hospitality suites. I had only one beer and six pieces of sushi before going to bed.

For the last 20 years, my routine for the beginning of the SPIE Advanced Lithography Symposium has been the same. Fly in to San Jose on Saturday, go out for a nice dinner with friends I haven’t seen in a while, and then teach a full-day short course on Sunday. This year that routine was interrupted by a 24-hour virus that hit me Saturday night. After a very unpleasant night, I spent Sunday in bed. To all those who signed up to take my course, possibly flying in a day early and taking up a precious weekend day to learn about lithography, I sincerely apologize.

Fortunately, the 24-hour bug is on schedule, and I feel well enough to attend the conference. Registration is up nearly 10% this year, continuing the five-year trend in growth for this conference. What can we expect to see this year? Of course, we all want to hear about progress in extreme ultraviolet (EUV) lithography. I expect the same result as last year: steady, but too slow. And what about the dark horse, directed self-assembly (DSA)? Progress on DSA over the last few years has been faster than I expected. Will that be true again this year? And after the interesting announcement 10 days ago that Cannon is buying Molecular Imprints, it will be interesting to hear about progress in nanoimprint lithography (NIL). I suspect, however, we won’t hear much on that front until next year, when the Toshiba-driven NIL development project comes to fruition.

The Bet. I regularly get questions about “the bet”. Five years ago at this conference I made a bet with Vivek Bakshi about when (or if) EUV would be used in manufacturing. The details are fuzzy (there was much beer involved), and Vivek and I don’t quite agree as to what we agreed to. Vivek said he thought EUV would be ready for manufacturing in 2013 – 2014. I said no way. Thus became the bet. I now claim victory, because I remember the bet as being EUV manufacturing in 2013. He remembers EUV by 2014, and so has ten more months to go. I’m willing to concede the disagreement on date, since it does not diminish my confidence in winning. And what will I win? That, too, is a bit fuzzy. I remember betting my Lotus, but don’t quite recall what Vivek put up. I’m sure we’ll figure it out by this time next year.

The Prediction. Last year I gave the Keynote talk at the Design for Manufacturability through Design-Process Integration conference. In that talk I predicted the end of Moore’s Law. Not exactly, news, I know. After all, to quote Gordon Moore, no exponential is forever. But I was specific in my prediction. Very specific. I predicted that Moore’s Law would end on Wednesday, Feb. 26, 2014, just before the poster session. With a prediction like that, only two outcomes are possible: I will forever more be consider a prescient sage, second only to Gordon Moore himself in my tech trend spotting abilities, or I’ll look like a fool. Personally, I’m OK either way. So if you are around, please join me Wednesday at the poster session where we’ll make a toast to the end of Moore’s Law.

Let the conference begin!

I’ve been teaching a class at the University of Texas at Austin giving an overview of the processes for semiconductor manufacturing for many years. This fall I did something different – I am flipped my classroom. I recorded each of my lectures ahead of time and required my students to watch the lectures before they came to class. Class time was then devoted to discussion, problem solving, and the occasional philosophical digression. While improvements will be necessary for the next year, the experiment was, I think, a success.

One outcome of the flipped classroom is a complete set of lectures for my class, available on YouTube. I have combined those lectures with reading and homework assignments as well as practice exams and other material. The result: a self-paced online course, available to anyone. I hope it will be the first of many.

The course name is Chemical Processes for Micro- and Nanofabrication (chemical engineering department, with course designator CHE323). It is basically an overview of all the process steps used in semiconductor manufacturing, with some nanofabrication concepts thrown in at the end. Here is the link:

http://www.lithoguru.com/scientist/CHE323/

Enjoy.

The Lithography Workshop, Nov. 10-14, 2013

I’ve just returned from a week in La Quinta, near Palm Springs, California. It is a desert of stark beauty: sand and mountains and incredible sunsets, out of which cities have risen, irrigating the desert into hiding. Palm trees and golf courses, adobe homes and strip malls, the grotesque surrounded by the sublime. And this week, a lithography conference as well.

The Lithography Workshop has been held every 18 months or so since 1981. I’ve attended about five of them (my first was in 1985 I think). They are purposefully modeled after the Gordon conferences, though they are more industrial than academic. There are presentations in the morning and in the evening, with afternoons free for socializing. They are always held in vacation destinations, and probably 20% of attendees come with their spouse.

Which is why the Lithography Workshop is commonly referred to as the Lithography Boondoggle. I suppose this nickname is deserved to certain extent, but the workshops are far from being a waste. This year there were 50 talks and about 15 posters, all of which were invited (I had a poster, but also subbed for a presenter who couldn't make it). As a result, the presenters are almost all seasoned experts, and a truly bad paper was hard to find. Without any publication of papers or presentations, the presenters are encouraged to be more open than they might otherwise be. Sure, some marketing messages crept into a few industry papers, and how can an ambitious academic help himself from indulging in self-promotion? Over all, though, the quality of the presentations was a noticeable step above most other conferences. That’s what makes it worthwhile to attend.

The downside of this all-invited format is an excessive abundance of establishment. Of the 120 attendees, a whopping six were women. I met two students, but almost everyone else looked like me – old and male and white. Granted, there is absolutely nothing wrong with looking like me (though one could aspire for better), I just don’t want everyone to look like me. It gets boring. But this is part of the nature of the Lithography Workshop. If I want to meet young, enthusiastic students I’ll go to the 3-beams conference. If I want to meet young, enthusiastic engineers just starting out in industry (as well as almost everyone else) I’ll go to the SPIE Advanced Lithography Symposium. But for a small conference full of senior lithographers, you can’t beat the Lithography Workshop.

The four plenary talks were all quite good. I especially liked hearing about Intel’s silicon photonics efforts (about to be commercialized), and learning what ARM thinks about lithography. I got an update on progress in DSA (directed self-assembly). Several people claimed DSA would go into production in 2014 (graphoepitaxy for contact holes), which shows a development pace that rivals that of immersion lithography a decade earlier. Updates from REBL and Mapper on their massively parallel electron beam lithography tools did not engender the same reaction. If DSA is a hare, multi-beam electron lithography is a tortoise. And somehow I don’t think this story will end the way Aesop intended.

Cymer and ASML gave updates on EUV lithography. I thought it was very telling when the Cymer presenter quipped that he was in front of a hostile crowd: lithographers. His presentation was mostly an overview of LPP sources, but he showed that they have achieved 50W operation for one hour, and have repeated this feat a few times. In February they had reached 40 W, so this appears to be quite slow progress. When asked about what source would be used in the currently shipping ASML NXE:3300B scanners, he repeated an obviously well-rehearsed line: we have committed to our customers to integrate an 80W source with the NXE:3300 in 2014.

So what does such a statement mean? Jos Benschop of ASML made it more clear in his presentation. There are currently 11 3300s in various stages of production. Three have gone through factory qualification and have been accepted by customers. Two have already been shipped to customer sites, and one is being packed up know, so I suspect three will have been shipped by the end of the year. These tools are being built with an older generation source (apparently the 10W version) and will be brought up at the customer site with that source. Then, when the 80W source is ready, this new source will be integrated into the 3300s in the field. From all indications, everything about the 3300 is ready except the source. Next year will be an important one for Cymer, and for ASML.

There was some good discussion about line-edge roughness (LER), always my favorite topic. I especially liked Jed Pitera’s take on LER from a material perspective rather than a lithography perspective. What are the fundamental limits? How low can LER go? I think the answer is not low enough. We are making progress on understanding LER if not on improving it.

But now my vacation, er, conference is over. I’ve caught up with several old friends, made a couple of new ones, and come away with several good ideas. The very definition of a successful conference.

Lithographers don't get to see me in a suit.

When I first started working in the semiconductor industry, I started out wearing a tie to conferences (I didn't own a suit back then), but quickly realized that not only were ties optional, you were better off not wearing them. Sales and marketing folks wore ties. To an engineer, wearing a tie made you suspect. I quickly ditched the ties.

Except in Japan. When I started traveling to Japan in the early 1990s, I bought some suits. Those are still my only suits (and they still fit ... barely). But I stopped wearing them 10 years ago even to Japan. The trend towards casual has caught up to the conservative corporate culture of Japan.

So, most of my friends in the lithography world have never seen me in a suit. Well, here is what it looks like.



I gave a talk last week at an investment banker conference in Hong Kong. Suit required. Someday maybe the finance folks will catch up to where lithographers have been all along.